diff options
| author | Hans Wennborg <hans@hanshq.net> | 2017-08-21 23:28:04 +0000 |
|---|---|---|
| committer | Hans Wennborg <hans@hanshq.net> | 2017-08-21 23:28:04 +0000 |
| commit | 94bd5ab1242b8157216400350f9d8dd55fa7dd72 (patch) | |
| tree | 0e4b5f3cd8e6aed53bce7a84f4ce7ed33f12645d /test | |
| parent | ef21e43d69b7dae3cff0f0524f53bf6821951dd6 (diff) | |
Merging r311071:
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r311071 | eladcohen | 2017-08-17 01:06:36 -0700 (Thu, 17 Aug 2017) | 13 lines
[SelectionDAG] Teach the vector-types operand scalarizer about SETCC
When v1i1 is legal (e.g. AVX512) the legalizer can reach
a case where a v1i1 SETCC with an illgeal vector type operand
wasn't scalarized (since v1i1 is legal) but its operands does
have to be scalarized. This used to assert because SETCC was
missing from the vector operand scalarizer.
This patch attemps to teach the legalizer to handle these cases
by scalazring the operands, converting the node into a scalar
SETCC node.
Differential revision: https://reviews.llvm.org/D36651
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git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@311409 91177308-0d34-0410-b5e6-96231b3b80d8
Diffstat (limited to 'test')
| -rw-r--r-- | test/CodeGen/X86/pr34177.ll | 52 |
1 files changed, 52 insertions, 0 deletions
diff --git a/test/CodeGen/X86/pr34177.ll b/test/CodeGen/X86/pr34177.ll new file mode 100644 index 000000000000..7c210058ae6c --- /dev/null +++ b/test/CodeGen/X86/pr34177.ll @@ -0,0 +1,52 @@ +; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py +; RUN: llc < %s -mattr=+avx512f | FileCheck %s +; RUN: llc < %s -mattr=+avx512f,+avx512vl,+avx512bw,+avx512dq | FileCheck %s + +target datalayout = "e-m:e-i64:64-f80:128-n8:16:32:64-S128" +target triple = "x86_64-unknown-linux-gnu" + +define void @test() local_unnamed_addr { +; CHECK-LABEL: test: +; CHECK: # BB#0: +; CHECK-NEXT: vmovdqa {{.*#+}} xmm0 = [2,3] +; CHECK-NEXT: vpextrq $1, %xmm0, %rax +; CHECK-NEXT: vmovq %xmm0, %rcx +; CHECK-NEXT: negq %rdx +; CHECK-NEXT: fld1 +; CHECK-NEXT: fldz +; CHECK-NEXT: fld %st(0) +; CHECK-NEXT: fcmove %st(2), %st(0) +; CHECK-NEXT: cmpq %rax, %rcx +; CHECK-NEXT: fld %st(1) +; CHECK-NEXT: fcmove %st(3), %st(0) +; CHECK-NEXT: cmpq %rax, %rax +; CHECK-NEXT: fld %st(2) +; CHECK-NEXT: fcmove %st(4), %st(0) +; CHECK-NEXT: movl $1, %eax +; CHECK-NEXT: cmpq %rax, %rax +; CHECK-NEXT: fld %st(3) +; CHECK-NEXT: fcmove %st(5), %st(0) +; CHECK-NEXT: fstp %st(5) +; CHECK-NEXT: fxch %st(2) +; CHECK-NEXT: fadd %st(3) +; CHECK-NEXT: fxch %st(4) +; CHECK-NEXT: fadd %st(3) +; CHECK-NEXT: fxch %st(2) +; CHECK-NEXT: fadd %st(3) +; CHECK-NEXT: fxch %st(1) +; CHECK-NEXT: faddp %st(3) +; CHECK-NEXT: fxch %st(3) +; CHECK-NEXT: fstpt (%rax) +; CHECK-NEXT: fxch %st(1) +; CHECK-NEXT: fstpt (%rax) +; CHECK-NEXT: fxch %st(1) +; CHECK-NEXT: fstpt (%rax) +; CHECK-NEXT: fstpt (%rax) + %1 = icmp eq <4 x i64> <i64 0, i64 1, i64 2, i64 3>, undef + %2 = select <4 x i1> %1, <4 x x86_fp80> <x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000, x86_fp80 0xK3FFF8000000000000000>, <4 x x86_fp80> zeroinitializer + %3 = fadd <4 x x86_fp80> undef, %2 + %4 = shufflevector <4 x x86_fp80> %3, <4 x x86_fp80> undef, <8 x i32> <i32 0, i32 4, i32 1, i32 5, i32 2, i32 6, i32 3, i32 7> + store <8 x x86_fp80> %4, <8 x x86_fp80>* undef, align 16 + unreachable +} + |