diff options
35 files changed, 40 insertions, 258 deletions
diff --git a/CMakeLists.txt b/CMakeLists.txt index c2ce41761b48..fe5343bcadd9 100644 --- a/CMakeLists.txt +++ b/CMakeLists.txt @@ -176,11 +176,6 @@ if(LLVM_DEPENDENCY_DEBUGGING) endif() endif() -option(LLVM_BUILD_GLOBAL_ISEL "Experimental: Build GlobalISel" ON) -if(LLVM_BUILD_GLOBAL_ISEL) - add_definitions(-DLLVM_BUILD_GLOBAL_ISEL) -endif() - option(LLVM_ENABLE_DAGISEL_COV "Debug: Prints tablegen patterns that were used for selecting" OFF) # Add path for custom modules diff --git a/lib/CodeGen/GlobalISel/CMakeLists.txt b/lib/CodeGen/GlobalISel/CMakeLists.txt index eba7ea8132e3..afe42b8cb84e 100644 --- a/lib/CodeGen/GlobalISel/CMakeLists.txt +++ b/lib/CodeGen/GlobalISel/CMakeLists.txt @@ -1,34 +1,21 @@ -# List of all GlobalISel files. -set(GLOBAL_ISEL_FILES - CallLowering.cpp - IRTranslator.cpp - InstructionSelect.cpp - InstructionSelector.cpp - MachineIRBuilder.cpp - LegalizerHelper.cpp - Legalizer.cpp - LegalizerInfo.cpp - Localizer.cpp - RegBankSelect.cpp - RegisterBank.cpp - RegisterBankInfo.cpp - Utils.cpp - ) - -# Add GlobalISel files to the dependencies if the user wants to build it. -if(LLVM_BUILD_GLOBAL_ISEL) - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) -else() - set(GLOBAL_ISEL_BUILD_FILES"") - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) -endif() - # In LLVMBuild.txt files, it is not possible to mark a dependency to a # library as optional. So instead, generate an empty library if we did # not ask for it. add_llvm_library(LLVMGlobalISel - ${GLOBAL_ISEL_BUILD_FILES} + CallLowering.cpp GlobalISel.cpp + IRTranslator.cpp + InstructionSelect.cpp + InstructionSelector.cpp + LegalizerHelper.cpp + Legalizer.cpp + LegalizerInfo.cpp + Localizer.cpp + MachineIRBuilder.cpp + RegBankSelect.cpp + RegisterBank.cpp + RegisterBankInfo.cpp + Utils.cpp DEPENDS intrinsics_gen diff --git a/lib/CodeGen/GlobalISel/GlobalISel.cpp b/lib/CodeGen/GlobalISel/GlobalISel.cpp index 29d1209bb02a..00c6a9d63158 100644 --- a/lib/CodeGen/GlobalISel/GlobalISel.cpp +++ b/lib/CodeGen/GlobalISel/GlobalISel.cpp @@ -16,13 +16,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL - -void llvm::initializeGlobalISel(PassRegistry &Registry) { -} - -#else - void llvm::initializeGlobalISel(PassRegistry &Registry) { initializeIRTranslatorPass(Registry); initializeLegalizerPass(Registry); @@ -30,4 +23,3 @@ void llvm::initializeGlobalISel(PassRegistry &Registry) { initializeRegBankSelectPass(Registry); initializeInstructionSelectPass(Registry); } -#endif // LLVM_BUILD_GLOBAL_ISEL diff --git a/lib/Target/AArch64/AArch64CallLowering.cpp b/lib/Target/AArch64/AArch64CallLowering.cpp index 29f6d571d6bd..fc09763ed387 100644 --- a/lib/Target/AArch64/AArch64CallLowering.cpp +++ b/lib/Target/AArch64/AArch64CallLowering.cpp @@ -47,10 +47,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "This shouldn't be built without GISel" -#endif - AArch64CallLowering::AArch64CallLowering(const AArch64TargetLowering &TLI) : CallLowering(&TLI) {} diff --git a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def index 8b1c9740d2ad..7d2cfbeff38a 100644 --- a/lib/Target/AArch64/AArch64GenRegisterBankInfo.def +++ b/lib/Target/AArch64/AArch64GenRegisterBankInfo.def @@ -11,10 +11,6 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - namespace llvm { RegisterBankInfo::PartialMapping AArch64GenRegisterBankInfo::PartMappings[]{ /* StartIdx, Length, RegBank */ diff --git a/lib/Target/AArch64/AArch64InstructionSelector.cpp b/lib/Target/AArch64/AArch64InstructionSelector.cpp index fb4d160718a1..d684578d2917 100644 --- a/lib/Target/AArch64/AArch64InstructionSelector.cpp +++ b/lib/Target/AArch64/AArch64InstructionSelector.cpp @@ -37,10 +37,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - namespace { #define GET_GLOBALISEL_PREDICATE_BITSET diff --git a/lib/Target/AArch64/AArch64LegalizerInfo.cpp b/lib/Target/AArch64/AArch64LegalizerInfo.cpp index 799240d9b3b7..34217d3447fa 100644 --- a/lib/Target/AArch64/AArch64LegalizerInfo.cpp +++ b/lib/Target/AArch64/AArch64LegalizerInfo.cpp @@ -23,10 +23,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - AArch64LegalizerInfo::AArch64LegalizerInfo() { using namespace TargetOpcode; const LLT p0 = LLT::pointer(0, 64); diff --git a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp index 69f3ff6cc8cb..2862644ceace 100644 --- a/lib/Target/AArch64/AArch64RegisterBankInfo.cpp +++ b/lib/Target/AArch64/AArch64RegisterBankInfo.cpp @@ -37,10 +37,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - AArch64RegisterBankInfo::AArch64RegisterBankInfo(const TargetRegisterInfo &TRI) : AArch64GenRegisterBankInfo() { static bool AlreadyInit = false; diff --git a/lib/Target/AArch64/AArch64Subtarget.cpp b/lib/Target/AArch64/AArch64Subtarget.cpp index 4880ff6f9e7b..4fb4991da696 100644 --- a/lib/Target/AArch64/AArch64Subtarget.cpp +++ b/lib/Target/AArch64/AArch64Subtarget.cpp @@ -18,7 +18,6 @@ #include "AArch64PBQPRegAlloc.h" #include "AArch64TargetMachine.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "AArch64CallLowering.h" #include "AArch64LegalizerInfo.h" #include "AArch64RegisterBankInfo.h" @@ -27,7 +26,6 @@ #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" -#endif #include "llvm/CodeGen/MachineScheduler.h" #include "llvm/IR/GlobalValue.h" #include "llvm/Support/TargetRegistry.h" @@ -143,7 +141,6 @@ void AArch64Subtarget::initializeProperties() { } } -#ifdef LLVM_BUILD_GLOBAL_ISEL namespace { struct AArch64GISelActualAccessor : public GISelAccessor { @@ -170,7 +167,6 @@ struct AArch64GISelActualAccessor : public GISelAccessor { }; } // end anonymous namespace -#endif AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, const std::string &FS, @@ -180,9 +176,6 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, IsLittle(LittleEndian), TargetTriple(TT), FrameLowering(), InstrInfo(initializeSubtargetDependencies(FS, CPU)), TSInfo(), TLInfo(TM, *this), GISel() { -#ifndef LLVM_BUILD_GLOBAL_ISEL - GISelAccessor *AArch64GISel = new GISelAccessor(); -#else AArch64GISelActualAccessor *AArch64GISel = new AArch64GISelActualAccessor(); AArch64GISel->CallLoweringInfo.reset( new AArch64CallLowering(*getTargetLowering())); @@ -197,7 +190,6 @@ AArch64Subtarget::AArch64Subtarget(const Triple &TT, const std::string &CPU, *static_cast<const AArch64TargetMachine *>(&TM), *this, *RBI)); AArch64GISel->RegBankInfo.reset(RBI); -#endif setGISelAccessor(*AArch64GISel); } diff --git a/lib/Target/AArch64/AArch64TargetMachine.cpp b/lib/Target/AArch64/AArch64TargetMachine.cpp index 14263d47b1ad..e65b382e85b2 100644 --- a/lib/Target/AArch64/AArch64TargetMachine.cpp +++ b/lib/Target/AArch64/AArch64TargetMachine.cpp @@ -330,13 +330,11 @@ public: void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override; -#ifdef LLVM_BUILD_GLOBAL_ISEL bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; void addPreGlobalInstructionSelect() override; bool addGlobalInstructionSelect() override; -#endif bool addILPOpts() override; void addPreRegAlloc() override; void addPostRegAlloc() override; @@ -432,7 +430,6 @@ bool AArch64PassConfig::addInstSelector() { return false; } -#ifdef LLVM_BUILD_GLOBAL_ISEL bool AArch64PassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; @@ -458,7 +455,6 @@ bool AArch64PassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); return false; } -#endif bool AArch64PassConfig::isGlobalISelEnabled() const { return TM->getOptLevel() <= EnableGlobalISelAtO; diff --git a/lib/Target/AArch64/CMakeLists.txt b/lib/Target/AArch64/CMakeLists.txt index f7e0a5c7bed3..eb1079be7300 100644 --- a/lib/Target/AArch64/CMakeLists.txt +++ b/lib/Target/AArch64/CMakeLists.txt @@ -13,34 +13,16 @@ tablegen(LLVM AArch64GenCallingConv.inc -gen-callingconv) tablegen(LLVM AArch64GenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM AArch64GenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM AArch64GenSystemOperands.inc -gen-searchable-tables) -if(LLVM_BUILD_GLOBAL_ISEL) - tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank) - tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel) -endif() +tablegen(LLVM AArch64GenRegisterBank.inc -gen-register-bank) +tablegen(LLVM AArch64GenGlobalISel.inc -gen-global-isel) add_public_tablegen_target(AArch64CommonTableGen) -# List of all GlobalISel files. -set(GLOBAL_ISEL_FILES - AArch64CallLowering.cpp - AArch64InstructionSelector.cpp - AArch64LegalizerInfo.cpp - AArch64RegisterBankInfo.cpp - ) - -# Add GlobalISel files to the dependencies if the user wants to build it. -if(LLVM_BUILD_GLOBAL_ISEL) - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) -else() - set(GLOBAL_ISEL_BUILD_FILES"") - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) -endif() - - add_llvm_target(AArch64CodeGen AArch64A57FPLoadBalancing.cpp AArch64AdvSIMDScalarPass.cpp AArch64AsmPrinter.cpp + AArch64CallLowering.cpp AArch64CleanupLocalDynamicTLSPass.cpp AArch64CollectLOH.cpp AArch64CondBrTuning.cpp @@ -56,11 +38,14 @@ add_llvm_target(AArch64CodeGen AArch64ISelDAGToDAG.cpp AArch64ISelLowering.cpp AArch64InstrInfo.cpp + AArch64InstructionSelector.cpp + AArch64LegalizerInfo.cpp AArch64LoadStoreOptimizer.cpp AArch64MacroFusion.cpp AArch64MCInstLower.cpp AArch64PromoteConstant.cpp AArch64PBQPRegAlloc.cpp + AArch64RegisterBankInfo.cpp AArch64RegisterInfo.cpp AArch64SelectionDAGInfo.cpp AArch64StorePairSuppress.cpp @@ -69,7 +54,6 @@ add_llvm_target(AArch64CodeGen AArch64TargetObjectFile.cpp AArch64TargetTransformInfo.cpp AArch64VectorByElementOpt.cpp - ${GLOBAL_ISEL_BUILD_FILES} DEPENDS intrinsics_gen diff --git a/lib/Target/AMDGPU/AMDGPUCallLowering.cpp b/lib/Target/AMDGPU/AMDGPUCallLowering.cpp index 31ae706d91d5..21aa0e592569 100644 --- a/lib/Target/AMDGPU/AMDGPUCallLowering.cpp +++ b/lib/Target/AMDGPU/AMDGPUCallLowering.cpp @@ -26,10 +26,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "This shouldn't be built without GISel" -#endif - AMDGPUCallLowering::AMDGPUCallLowering(const AMDGPUTargetLowering &TLI) : CallLowering(&TLI), AMDGPUASI(TLI.getAMDGPUAS()) { } diff --git a/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def b/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def index 5cb9036f4823..bf7deb500d1a 100644 --- a/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def +++ b/lib/Target/AMDGPU/AMDGPUGenRegisterBankInfo.def @@ -11,10 +11,6 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - namespace llvm { namespace AMDGPU { diff --git a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp index 7d7848cf9164..9dc03a541586 100644 --- a/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPULegalizerInfo.cpp @@ -21,10 +21,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - AMDGPULegalizerInfo::AMDGPULegalizerInfo() { using namespace TargetOpcode; diff --git a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp index 623b2c88ab8f..a1156e20c304 100644 --- a/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp +++ b/lib/Target/AMDGPU/AMDGPURegisterBankInfo.cpp @@ -29,10 +29,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - AMDGPURegisterBankInfo::AMDGPURegisterBankInfo(const TargetRegisterInfo &TRI) : AMDGPUGenRegisterBankInfo(), TRI(static_cast<const SIRegisterInfo*>(&TRI)) { diff --git a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp index f4484b9c653e..85ff5b325073 100644 --- a/lib/Target/AMDGPU/AMDGPUSubtarget.cpp +++ b/lib/Target/AMDGPU/AMDGPUSubtarget.cpp @@ -15,12 +15,10 @@ #include "AMDGPUSubtarget.h" #include "AMDGPU.h" #include "AMDGPUTargetMachine.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "AMDGPUCallLowering.h" #include "AMDGPUInstructionSelector.h" #include "AMDGPULegalizerInfo.h" #include "AMDGPURegisterBankInfo.h" -#endif #include "SIMachineFunctionInfo.h" #include "llvm/ADT/SmallString.h" #include "llvm/CodeGen/MachineScheduler.h" @@ -80,7 +78,6 @@ AMDGPUSubtarget::initializeSubtargetDependencies(const Triple &TT, return *this; } -#ifdef LLVM_BUILD_GLOBAL_ISEL namespace { struct SIGISelActualAccessor : public GISelAccessor { @@ -103,7 +100,6 @@ struct SIGISelActualAccessor : public GISelAccessor { }; } // end anonymous namespace -#endif AMDGPUSubtarget::AMDGPUSubtarget(const Triple &TT, StringRef GPU, StringRef FS, const TargetMachine &TM) @@ -358,9 +354,6 @@ SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS, : AMDGPUSubtarget(TT, GPU, FS, TM), InstrInfo(*this), FrameLowering(TargetFrameLowering::StackGrowsUp, getStackAlignment(), 0), TLInfo(TM, *this) { -#ifndef LLVM_BUILD_GLOBAL_ISEL - GISelAccessor *GISel = new GISelAccessor(); -#else SIGISelActualAccessor *GISel = new SIGISelActualAccessor(); GISel->CallLoweringInfo.reset(new AMDGPUCallLowering(*getTargetLowering())); GISel->Legalizer.reset(new AMDGPULegalizerInfo()); @@ -368,7 +361,6 @@ SISubtarget::SISubtarget(const Triple &TT, StringRef GPU, StringRef FS, GISel->RegBankInfo.reset(new AMDGPURegisterBankInfo(*getRegisterInfo())); GISel->InstSelector.reset(new AMDGPUInstructionSelector( *this, *static_cast<AMDGPURegisterBankInfo *>(GISel->RegBankInfo.get()))); -#endif setGISelAccessor(*GISel); } diff --git a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp index e3f8dc15bd23..41b4f7082d68 100644 --- a/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp +++ b/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp @@ -516,12 +516,10 @@ public: void addMachineSSAOptimization() override; bool addILPOpts() override; bool addInstSelector() override; -#ifdef LLVM_BUILD_GLOBAL_ISEL bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; -#endif void addFastRegAlloc(FunctionPass *RegAllocPass) override; void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override; void addPreRegAlloc() override; @@ -756,7 +754,6 @@ bool GCNPassConfig::addInstSelector() { return false; } -#ifdef LLVM_BUILD_GLOBAL_ISEL bool GCNPassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; @@ -777,8 +774,6 @@ bool GCNPassConfig::addGlobalInstructionSelect() { return false; } -#endif - void GCNPassConfig::addPreRegAlloc() { if (LateCFGStructurize) { addPass(createAMDGPUMachineCFGStructurizerPass()); diff --git a/lib/Target/AMDGPU/CMakeLists.txt b/lib/Target/AMDGPU/CMakeLists.txt index ead789856dc4..75c6fc4e5099 100644 --- a/lib/Target/AMDGPU/CMakeLists.txt +++ b/lib/Target/AMDGPU/CMakeLists.txt @@ -12,28 +12,9 @@ tablegen(LLVM AMDGPUGenAsmWriter.inc -gen-asm-writer) tablegen(LLVM AMDGPUGenAsmMatcher.inc -gen-asm-matcher) tablegen(LLVM AMDGPUGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM AMDGPUGenMCPseudoLowering.inc -gen-pseudo-lowering) -if(LLVM_BUILD_GLOBAL_ISEL) - tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank) -endif() +tablegen(LLVM AMDGPUGenRegisterBank.inc -gen-register-bank) add_public_tablegen_target(AMDGPUCommonTableGen) -# List of all GlobalISel files. -set(GLOBAL_ISEL_FILES - AMDGPUCallLowering.cpp - AMDGPUInstructionSelector.cpp - AMDGPULegalizerInfo.cpp - AMDGPURegisterBankInfo.cpp - ) - -# Add GlobalISel files to the dependencies if the user wants to build it. -if(LLVM_BUILD_GLOBAL_ISEL) - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) -else() - set(GLOBAL_ISEL_BUILD_FILES"") - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) -endif() - - add_llvm_target(AMDGPUCodeGen AMDILCFGStructurizer.cpp AMDGPUAliasAnalysis.cpp @@ -41,9 +22,12 @@ add_llvm_target(AMDGPUCodeGen AMDGPUAnnotateKernelFeatures.cpp AMDGPUAnnotateUniformValues.cpp AMDGPUAsmPrinter.cpp + AMDGPUCallLowering.cpp AMDGPUCodeGenPrepare.cpp AMDGPUFrameLowering.cpp + AMDGPULegalizerInfo.cpp AMDGPUTargetObjectFile.cpp + AMDGPUInstructionSelector.cpp AMDGPUIntrinsicInfo.cpp AMDGPUISelDAGToDAG.cpp AMDGPULowerIntrinsics.cpp @@ -61,6 +45,7 @@ add_llvm_target(AMDGPUCodeGen AMDGPUInstrInfo.cpp AMDGPUPromoteAlloca.cpp AMDGPURegAsmNames.inc.cpp + AMDGPURegisterBankInfo.cpp AMDGPURegisterInfo.cpp AMDGPURewriteOutArguments.cpp AMDGPUUnifyDivergentExitNodes.cpp @@ -105,7 +90,6 @@ add_llvm_target(AMDGPUCodeGen GCNIterativeScheduler.cpp GCNMinRegStrategy.cpp GCNRegPressure.cpp - ${GLOBAL_ISEL_BUILD_FILES} ) add_subdirectory(AsmParser) diff --git a/lib/Target/ARM/ARMCallLowering.cpp b/lib/Target/ARM/ARMCallLowering.cpp index 051827a6a6a2..e2671dfccd92 100644 --- a/lib/Target/ARM/ARMCallLowering.cpp +++ b/lib/Target/ARM/ARMCallLowering.cpp @@ -26,10 +26,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "This shouldn't be built without GISel" -#endif - ARMCallLowering::ARMCallLowering(const ARMTargetLowering &TLI) : CallLowering(&TLI) {} diff --git a/lib/Target/ARM/ARMInstructionSelector.cpp b/lib/Target/ARM/ARMInstructionSelector.cpp index 6364ffbc753a..0d74fca5db98 100644 --- a/lib/Target/ARM/ARMInstructionSelector.cpp +++ b/lib/Target/ARM/ARMInstructionSelector.cpp @@ -25,10 +25,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - namespace { #define GET_GLOBALISEL_PREDICATE_BITSET diff --git a/lib/Target/ARM/ARMLegalizerInfo.cpp b/lib/Target/ARM/ARMLegalizerInfo.cpp index 2302e7e6e238..8185f8acc921 100644 --- a/lib/Target/ARM/ARMLegalizerInfo.cpp +++ b/lib/Target/ARM/ARMLegalizerInfo.cpp @@ -24,10 +24,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - static bool AEABI(const ARMSubtarget &ST) { return ST.isTargetAEABI() || ST.isTargetGNUAEABI() || ST.isTargetMuslAEABI(); } diff --git a/lib/Target/ARM/ARMRegisterBankInfo.cpp b/lib/Target/ARM/ARMRegisterBankInfo.cpp index 8bb58c3c452f..84d6be63cbec 100644 --- a/lib/Target/ARM/ARMRegisterBankInfo.cpp +++ b/lib/Target/ARM/ARMRegisterBankInfo.cpp @@ -24,10 +24,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - // FIXME: TableGen this. // If it grows too much and TableGen still isn't ready to do the job, extract it // into an ARMGenRegisterBankInfo.def (similar to AArch64). diff --git a/lib/Target/ARM/ARMSubtarget.cpp b/lib/Target/ARM/ARMSubtarget.cpp index 78bcbb77029e..29d6d148d913 100644 --- a/lib/Target/ARM/ARMSubtarget.cpp +++ b/lib/Target/ARM/ARMSubtarget.cpp @@ -13,11 +13,9 @@ #include "ARM.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "ARMCallLowering.h" #include "ARMLegalizerInfo.h" #include "ARMRegisterBankInfo.h" -#endif #include "ARMSubtarget.h" #include "ARMFrameLowering.h" #include "ARMInstrInfo.h" @@ -30,13 +28,11 @@ #include "llvm/ADT/StringRef.h" #include "llvm/ADT/Triple.h" #include "llvm/ADT/Twine.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "llvm/CodeGen/GlobalISel/GISelAccessor.h" #include "llvm/CodeGen/GlobalISel/IRTranslator.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" -#endif #include "llvm/CodeGen/MachineFunction.h" #include "llvm/IR/Function.h" #include "llvm/IR/GlobalValue.h" @@ -101,7 +97,6 @@ ARMFrameLowering *ARMSubtarget::initializeFrameLowering(StringRef CPU, return new ARMFrameLowering(STI); } -#ifdef LLVM_BUILD_GLOBAL_ISEL namespace { struct ARMGISelActualAccessor : public GISelAccessor { @@ -128,7 +123,6 @@ struct ARMGISelActualAccessor : public GISelAccessor { }; } // end anonymous namespace -#endif ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, const std::string &FS, @@ -147,9 +141,6 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, assert((isThumb() || hasARMOps()) && "Target must either be thumb or support ARM operations!"); -#ifndef LLVM_BUILD_GLOBAL_ISEL - GISelAccessor *GISel = new GISelAccessor(); -#else ARMGISelActualAccessor *GISel = new ARMGISelActualAccessor(); GISel->CallLoweringInfo.reset(new ARMCallLowering(*getTargetLowering())); GISel->Legalizer.reset(new ARMLegalizerInfo(*this)); @@ -163,7 +154,6 @@ ARMSubtarget::ARMSubtarget(const Triple &TT, const std::string &CPU, *static_cast<const ARMBaseTargetMachine *>(&TM), *this, *RBI)); GISel->RegBankInfo.reset(RBI); -#endif setGISelAccessor(*GISel); } diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index eaab7331e348..d68ffa2313c8 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -333,12 +333,10 @@ public: void addIRPasses() override; bool addPreISel() override; bool addInstSelector() override; -#ifdef LLVM_BUILD_GLOBAL_ISEL bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; -#endif void addPreRegAlloc() override; void addPreSched2() override; void addPreEmitPass() override; @@ -413,7 +411,6 @@ bool ARMPassConfig::addInstSelector() { return false; } -#ifdef LLVM_BUILD_GLOBAL_ISEL bool ARMPassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; @@ -433,7 +430,6 @@ bool ARMPassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); return false; } -#endif void ARMPassConfig::addPreRegAlloc() { if (getOptLevel() != CodeGenOpt::None) { diff --git a/lib/Target/ARM/CMakeLists.txt b/lib/Target/ARM/CMakeLists.txt index 8909ddf71ee9..014ac2ae8b48 100644 --- a/lib/Target/ARM/CMakeLists.txt +++ b/lib/Target/ARM/CMakeLists.txt @@ -1,9 +1,7 @@ set(LLVM_TARGET_DEFINITIONS ARM.td) -if(LLVM_BUILD_GLOBAL_ISEL) - tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank) - tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel) -endif() +tablegen(LLVM ARMGenRegisterBank.inc -gen-register-bank) +tablegen(LLVM ARMGenGlobalISel.inc -gen-global-isel) tablegen(LLVM ARMGenRegisterInfo.inc -gen-register-info) tablegen(LLVM ARMGenInstrInfo.inc -gen-instr-info) tablegen(LLVM ARMGenMCCodeEmitter.inc -gen-emitter) @@ -18,41 +16,30 @@ tablegen(LLVM ARMGenDisassemblerTables.inc -gen-disassembler) tablegen(LLVM ARMGenSystemRegister.inc -gen-searchable-tables) add_public_tablegen_target(ARMCommonTableGen) -# Add GlobalISel files if the user wants to build it. -set(GLOBAL_ISEL_FILES - ARMCallLowering.cpp - ARMInstructionSelector.cpp - ARMLegalizerInfo.cpp - ARMRegisterBankInfo.cpp - ) - -if(LLVM_BUILD_GLOBAL_ISEL) - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) -else() - set(GLOBAL_ISEL_BUILD_FILES "") - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) -endif() - add_llvm_target(ARMCodeGen A15SDOptimizer.cpp ARMAsmPrinter.cpp ARMBaseInstrInfo.cpp ARMBaseRegisterInfo.cpp + ARMCallLowering.cpp ARMConstantIslandPass.cpp ARMConstantPoolValue.cpp ARMExpandPseudoInsts.cpp ARMFastISel.cpp ARMFrameLowering.cpp ARMHazardRecognizer.cpp + ARMInstructionSelector.cpp ARMISelDAGToDAG.cpp ARMISelLowering.cpp ARMInstrInfo.cpp + ARMLegalizerInfo.cpp ARMLoadStoreOptimizer.cpp ARMMCInstLower.cpp ARMMachineFunctionInfo.cpp ARMMacroFusion.cpp ARMRegisterInfo.cpp ARMOptimizeBarriersPass.cpp + ARMRegisterBankInfo.cpp ARMSelectionDAGInfo.cpp ARMSubtarget.cpp ARMTargetMachine.cpp @@ -66,7 +53,6 @@ add_llvm_target(ARMCodeGen Thumb2InstrInfo.cpp Thumb2SizeReduction.cpp ARMComputeBlockSize.cpp - ${GLOBAL_ISEL_BUILD_FILES} ) add_subdirectory(TargetInfo) diff --git a/lib/Target/X86/CMakeLists.txt b/lib/Target/X86/CMakeLists.txt index 6e08d4cff6ea..3966581d9352 100644 --- a/lib/Target/X86/CMakeLists.txt +++ b/lib/Target/X86/CMakeLists.txt @@ -11,32 +11,15 @@ tablegen(LLVM X86GenFastISel.inc -gen-fast-isel) tablegen(LLVM X86GenCallingConv.inc -gen-callingconv) tablegen(LLVM X86GenSubtargetInfo.inc -gen-subtarget) tablegen(LLVM X86GenEVEX2VEXTables.inc -gen-x86-EVEX2VEX-tables) -if(LLVM_BUILD_GLOBAL_ISEL) - tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank) - tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel) -endif() +tablegen(LLVM X86GenRegisterBank.inc -gen-register-bank) +tablegen(LLVM X86GenGlobalISel.inc -gen-global-isel) add_public_tablegen_target(X86CommonTableGen) -# Add GlobalISel files if the build option was enabled. -set(GLOBAL_ISEL_FILES - X86CallLowering.cpp - X86LegalizerInfo.cpp - X86RegisterBankInfo.cpp - X86InstructionSelector.cpp - ) - -if(LLVM_BUILD_GLOBAL_ISEL) - set(GLOBAL_ISEL_BUILD_FILES ${GLOBAL_ISEL_FILES}) -else() - set(GLOBAL_ISEL_BUILD_FILES "") - set(LLVM_OPTIONAL_SOURCES LLVMGlobalISel ${GLOBAL_ISEL_FILES}) -endif() - - set(sources X86AsmPrinter.cpp X86CallFrameOptimization.cpp + X86CallLowering.cpp X86CmovConversion.cpp X86ExpandPseudo.cpp X86FastISel.cpp @@ -45,17 +28,20 @@ set(sources X86FixupSetCC.cpp X86FloatingPoint.cpp X86FrameLowering.cpp + X86InstructionSelector.cpp X86ISelDAGToDAG.cpp X86ISelLowering.cpp X86InterleavedAccess.cpp X86InstrFMA3Info.cpp X86InstrInfo.cpp X86EvexToVex.cpp + X86LegalizerInfo.cpp X86MCInstLower.cpp X86MachineFunctionInfo.cpp X86MacroFusion.cpp X86OptimizeLEAs.cpp X86PadShortFunction.cpp + X86RegisterBankInfo.cpp X86RegisterInfo.cpp X86SelectionDAGInfo.cpp X86ShuffleDecodeConstantPool.cpp @@ -67,7 +53,6 @@ set(sources X86WinAllocaExpander.cpp X86WinEHState.cpp X86CallingConv.cpp - ${GLOBAL_ISEL_BUILD_FILES} ) add_llvm_target(X86CodeGen ${sources}) diff --git a/lib/Target/X86/X86CallLowering.cpp b/lib/Target/X86/X86CallLowering.cpp index 99aeec67c326..c8a3b2b51c88 100644 --- a/lib/Target/X86/X86CallLowering.cpp +++ b/lib/Target/X86/X86CallLowering.cpp @@ -29,10 +29,6 @@ using namespace llvm; #include "X86GenCallingConv.inc" -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "This shouldn't be built without GISel" -#endif - X86CallLowering::X86CallLowering(const X86TargetLowering &TLI) : CallLowering(&TLI) {} diff --git a/lib/Target/X86/X86GenRegisterBankInfo.def b/lib/Target/X86/X86GenRegisterBankInfo.def index 06be142432f7..9cd3f96f83ac 100644 --- a/lib/Target/X86/X86GenRegisterBankInfo.def +++ b/lib/Target/X86/X86GenRegisterBankInfo.def @@ -11,10 +11,6 @@ /// \todo This should be generated by TableGen. //===----------------------------------------------------------------------===// -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - #ifdef GET_TARGET_REGBANK_INFO_IMPL RegisterBankInfo::PartialMapping X86GenRegisterBankInfo::PartMappings[]{ /* StartIdx, Length, RegBank */ diff --git a/lib/Target/X86/X86InstructionSelector.cpp b/lib/Target/X86/X86InstructionSelector.cpp index 859d3288db89..5801163573b5 100644 --- a/lib/Target/X86/X86InstructionSelector.cpp +++ b/lib/Target/X86/X86InstructionSelector.cpp @@ -36,10 +36,6 @@ using namespace llvm; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - namespace { #define GET_GLOBALISEL_PREDICATE_BITSET diff --git a/lib/Target/X86/X86LegalizerInfo.cpp b/lib/Target/X86/X86LegalizerInfo.cpp index 744ba21011af..b1075995be29 100644 --- a/lib/Target/X86/X86LegalizerInfo.cpp +++ b/lib/Target/X86/X86LegalizerInfo.cpp @@ -22,10 +22,6 @@ using namespace llvm; using namespace TargetOpcode; -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - X86LegalizerInfo::X86LegalizerInfo(const X86Subtarget &STI, const X86TargetMachine &TM) : Subtarget(STI), TM(TM) { diff --git a/lib/Target/X86/X86RegisterBankInfo.cpp b/lib/Target/X86/X86RegisterBankInfo.cpp index efd3df26dd42..ec303aca9c8a 100644 --- a/lib/Target/X86/X86RegisterBankInfo.cpp +++ b/lib/Target/X86/X86RegisterBankInfo.cpp @@ -26,10 +26,6 @@ using namespace llvm; #define GET_TARGET_REGBANK_INFO_IMPL #include "X86GenRegisterBankInfo.def" -#ifndef LLVM_BUILD_GLOBAL_ISEL -#error "You shouldn't build this" -#endif - X86RegisterBankInfo::X86RegisterBankInfo(const TargetRegisterInfo &TRI) : X86GenRegisterBankInfo() { diff --git a/lib/Target/X86/X86Subtarget.cpp b/lib/Target/X86/X86Subtarget.cpp index ea921cfac23b..0c8d2cb10bcc 100644 --- a/lib/Target/X86/X86Subtarget.cpp +++ b/lib/Target/X86/X86Subtarget.cpp @@ -13,21 +13,17 @@ #include "X86.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "X86CallLowering.h" #include "X86LegalizerInfo.h" #include "X86RegisterBankInfo.h" -#endif #include "X86Subtarget.h" #include "MCTargetDesc/X86BaseInfo.h" #include "X86TargetMachine.h" #include "llvm/ADT/Triple.h" -#ifdef LLVM_BUILD_GLOBAL_ISEL #include "llvm/CodeGen/GlobalISel/CallLowering.h" #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" #include "llvm/CodeGen/GlobalISel/Legalizer.h" #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" -#endif #include "llvm/IR/Attributes.h" #include "llvm/IR/ConstantRange.h" #include "llvm/IR/Function.h" @@ -352,7 +348,6 @@ X86Subtarget &X86Subtarget::initializeSubtargetDependencies(StringRef CPU, return *this; } -#ifdef LLVM_BUILD_GLOBAL_ISEL namespace { struct X86GISelActualAccessor : public GISelAccessor { @@ -379,7 +374,6 @@ struct X86GISelActualAccessor : public GISelAccessor { }; } // end anonymous namespace -#endif X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, const X86TargetMachine &TM, @@ -405,9 +399,6 @@ X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, setPICStyle(PICStyles::StubPIC); else if (isTargetELF()) setPICStyle(PICStyles::GOT); -#ifndef LLVM_BUILD_GLOBAL_ISEL - GISelAccessor *GISel = new GISelAccessor(); -#else X86GISelActualAccessor *GISel = new X86GISelActualAccessor(); GISel->CallLoweringInfo.reset(new X86CallLowering(*getTargetLowering())); @@ -416,7 +407,6 @@ X86Subtarget::X86Subtarget(const Triple &TT, StringRef CPU, StringRef FS, auto *RBI = new X86RegisterBankInfo(*getRegisterInfo()); GISel->RegBankInfo.reset(RBI); GISel->InstSelector.reset(createX86InstructionSelector(TM, *this, *RBI)); -#endif setGISelAccessor(*GISel); } diff --git a/lib/Target/X86/X86TargetMachine.cpp b/lib/Target/X86/X86TargetMachine.cpp index e40481dad34c..f071d229d896 100644 --- a/lib/Target/X86/X86TargetMachine.cpp +++ b/lib/Target/X86/X86TargetMachine.cpp @@ -306,12 +306,10 @@ public: void addIRPasses() override; bool addInstSelector() override; -#ifdef LLVM_BUILD_GLOBAL_ISEL bool addIRTranslator() override; bool addLegalizeMachineIR() override; bool addRegBankSelect() override; bool addGlobalInstructionSelect() override; -#endif bool addILPOpts() override; bool addPreISel() override; void addPreRegAlloc() override; @@ -361,7 +359,6 @@ bool X86PassConfig::addInstSelector() { return false; } -#ifdef LLVM_BUILD_GLOBAL_ISEL bool X86PassConfig::addIRTranslator() { addPass(new IRTranslator()); return false; @@ -381,7 +378,6 @@ bool X86PassConfig::addGlobalInstructionSelect() { addPass(new InstructionSelect()); return false; } -#endif bool X86PassConfig::addILPOpts() { addPass(&EarlyIfConverterID); diff --git a/tools/llvm-config/CMakeLists.txt b/tools/llvm-config/CMakeLists.txt index 5d48618c0610..25f99cec9788 100644 --- a/tools/llvm-config/CMakeLists.txt +++ b/tools/llvm-config/CMakeLists.txt @@ -37,11 +37,7 @@ set(LLVM_CXXFLAGS "${CMAKE_CXX_FLAGS} ${CMAKE_CXX_FLAGS_${uppercase_CMAKE_BUILD_ set(LLVM_BUILD_SYSTEM cmake) set(LLVM_HAS_RTTI ${LLVM_CONFIG_HAS_RTTI}) set(LLVM_DYLIB_VERSION "${LLVM_VERSION_MAJOR}.${LLVM_VERSION_MINOR}${LLVM_VERSION_SUFFIX}") -if(LLVM_BUILD_GLOBAL_ISEL) - set(LLVM_HAS_GLOBAL_ISEL "ON") -else() - set(LLVM_HAS_GLOBAL_ISEL "OFF") -endif() +set(LLVM_HAS_GLOBAL_ISEL "ON") # Use the C++ link flags, since they should be a superset of C link flags. set(LLVM_LDFLAGS "${CMAKE_CXX_LINK_FLAGS}") diff --git a/unittests/CodeGen/GlobalISel/CMakeLists.txt b/unittests/CodeGen/GlobalISel/CMakeLists.txt index 94e31159c6bb..075bb44bc330 100644 --- a/unittests/CodeGen/GlobalISel/CMakeLists.txt +++ b/unittests/CodeGen/GlobalISel/CMakeLists.txt @@ -3,8 +3,6 @@ set(LLVM_LINK_COMPONENTS CodeGen ) -if(LLVM_BUILD_GLOBAL_ISEL) - add_llvm_unittest(GlobalISelTests - LegalizerInfoTest.cpp - ) -endif() +add_llvm_unittest(GlobalISelTests + LegalizerInfoTest.cpp + ) |