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* WIP: Clang: Add patch to build static libclangrelease_50-basedIvan Donchevskii2019-03-211-1/+1
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* Merging r312509:Tom Stellard2017-12-062-7/+58
| | | | | | | | | | ------------------------------------------------------------------------ r312509 | dannyb | 2017-09-04 19:17:42 -0700 (Mon, 04 Sep 2017) | 1 line NewGVN: Fix PR 34452 by passing instruction all the way down when we do aggregate value simplification ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@319952 91177308-0d34-0410-b5e6-96231b3b80d8
* bpf: fix bug on silently truncating 64-bit immediateYonghong Song2017-12-033-3/+42
| | | | | | | | | | | | | | | | | | | | | | | | | | | We came across an llvm bug when compiling some testcases that 64-bit immediates are silently truncated into 32-bit and then packed into BPF_JMP | BPF_K encoding. This caused comparison with wrong value. This bug looks to be introduced by r308080 (llvm 5.0). The Select_Ri pattern is supposed to be lowered into J*_Ri while the latter only support 32-bit immediate encoding, therefore Select_Ri should have similar immediate predicate check as what J*_Ri are doing. The bug is fixed by git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@315889 91177308-0d34-0410-b5e6-96231b3b80d8 in llvm 6.0. This patch is largely the same as the fix in llvm 6.0 except one minor adjustment for the test case. Reported-by: John Fastabend <john.fastabend@gmail.com> Reported-by: Jakub Kicinski <jakub.kicinski@netronome.com> Signed-off-by: Jiong Wang <jiong.wang@netronome.com> Reviewed-by: Yonghong Song <yhs@fb.com> git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@319633 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r316035:Tom Stellard2017-11-283-0/+28
| | | | | | | | | | | | | | | ------------------------------------------------------------------------ r316035 | tnorthover | 2017-10-17 14:43:52 -0700 (Tue, 17 Oct 2017) | 6 lines AArch64: account for possible frame index operand in compares. If the address of a local is used in a comparison, AArch64 can fold the address-calculation into the comparison via "adds". Unfortunately, a couple of places (both hit in this one test) are not ready to deal with that yet and just assume the first source operand is a register. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@319231 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r319130:Tom Stellard2017-11-282-1/+28
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r319130 | matze | 2017-11-27 17:17:52 -0800 (Mon, 27 Nov 2017) | 7 lines ARM: Fix PR32578 https://llvm.org/PR32578 I simplified and converted the reproducer into a lit test. Patch by Vedant Kumar! ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@319181 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r318788:Tom Stellard2017-11-222-62/+1
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r318788 | mcrosier | 2017-11-21 10:08:34 -0800 (Tue, 21 Nov 2017) | 16 lines [AArch64] Mark mrs of TPIDR_EL0 (thread pointer) as *having* side effects. This partially reverts r298851. The the underlying issue is that we don't currently model the dependency between mrs (read system register) and msr (write system register) instructions. Something like the below should never be reordered: msr TPIDR_EL0, x0 ;; set thread pointer mrs x8, TPIDR_EL0 ;; read thread pointer but was being reordered after r298851. The functional part of the patch that wasn't reverted needed to remain in place in order to not break r299462. PR35317 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318854 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r315086:Tom Stellard2017-11-225-1/+64
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r315086 | compnerd | 2017-10-06 11:06:59 -0700 (Fri, 06 Oct 2017) | 8 lines Bitcode: add an auto-upgrade for LTO section name The bitcode reader looks specifically for `__DATA, __objc_catlist` as a section name. However, SVN r304661 removed the spaces (the two names are functionally equivalent but do not compare equally lexicographically). This causes compatibility issues. Add an auto-upgrade path for removing the spaces as well as use the new name in the LTO plugin. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318851 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r313398:Tom Stellard2017-11-222-2/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r313398 | steven_wu | 2017-09-15 14:12:14 -0700 (Fri, 15 Sep 2017) | 19 lines [AutoUpgrade] Fix a compatibility issue with module flag Summary: After r304661, module flag to record objective-c image info section is encoded without whitespaces after comma. The new name is equivalent to the old one, except that when LTO a module built by old compiler and a module built by a new compiler, it will fail with conflicting values. Fix the issue by removing whitespaces in bitcode upgrade path. rdar://problem/34416934 Reviewers: compnerd Reviewed By: compnerd Subscribers: mehdi_amini, hans, llvm-commits Differential Revision: https://reviews.llvm.org/D37909 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318850 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r318289:Tom Stellard2017-11-173-8/+67
| | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r318289 | jdevlieghere | 2017-11-15 02:57:05 -0800 (Wed, 15 Nov 2017) | 14 lines [DebugInfo] Fix potential CU mismatch for SubprogramScopeDIEs. In constructAbstractSubprogramScopeDIE there can be a potential mismatch between `this` and the CU of ContextDIE when a scope is shared between two DISubprograms belonging to a different CU. In that case, `this` is the CU that was specified in the IR, but the CU of ContextDIE is that of the first subprogram that was emitted. This patch fixes the mismatch by looking up the CU of ContextDIE, and switching to use that. This fixes PR35212 (https://bugs.llvm.org/show_bug.cgi?id=35212) Patch by Philip Craig! Differential revision: https://reviews.llvm.org/D39981 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318542 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r318207:Simon Dardis2017-11-1616-14/+547
| | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r318207 | sdardis | 2017-11-14 22:26:42 +0000 (Tue, 14 Nov 2017) | 18 lines Reland "[mips][mt][6/7] Add support for mftr, mttr instructions." This adjusts the tests to hopfully pacify the llvm-clang-x86_64-expensive-checks-win buildbot. Unlike many other instructions, these instructions have aliases which take coprocessor registers, gpr register, accumulator (and dsp accumulator) registers, floating point registers, floating point control registers and coprocessor 2 data and control operands. For the moment, these aliases are treated as pseudo instructions which are expanded into the underlying instruction. As a result, disassembling these instructions shows the underlying instruction and not the alias. Reviewers: slthakur, atanasyan Differential Revision: https://reviews.llvm.org/D35253 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318386 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312043:Tom Stellard2017-11-152-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312043 | rnk | 2017-08-29 14:44:21 -0700 (Tue, 29 Aug 2017) | 25 lines [cmake] Stop putting the revision info in LLVM_VERSION_STRING Summary: This reduces the number of build actions after a no-op commit from thousands to about six, which should be acceptable. If six actions is still too many, developers can disable the LLVM_APPEND_VC_REV cmake option. llvm-config.h is a widely included header that should rarely change. Before this patch, it would change after every re-configure. Very few users of llvm-config.h need to know the precise version, and those that do can migrate to incorporating LLVM_REVISION as provided by llvm/Support/VCSRevision.h. This should bring LLVM back to the behavior that it had before r306858 from June 30 2017. Most LLVM tools will now print a version string like "6.0.0svn" instead of "6.0.0-git-c40c2a23de4". Fixes PR34308 Reviewers: pcc, rafael, hans Subscribers: mgorny, llvm-commits Differential Revision: https://reviews.llvm.org/D37272 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318344 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r310475:Tom Stellard2017-11-152-0/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r310475 | belleyb | 2017-08-09 06:47:01 -0700 (Wed, 09 Aug 2017) | 28 lines [Support] PR33388 - Fix formatv_object move constructor formatv_object currently uses the implicitly defined move constructor, but it is buggy. In typical use-cases, the problem doesn't show-up because all calls to the move constructor are elided. Thus, the buggy constructors are never invoked. The issue especially shows-up when code is compiled using the -fno-elide-constructors compiler flag. For instance, this is useful when attempting to collect accurate code coverage statistics. The exact issue is the following: The Parameters data member is correctly moved, thus making the parameters occupy a new memory location in the target object. Unfortunately, the default copying of the Adapters blindly copies the vector of pointers, leaving each of these pointers referencing the parameters in the original object instead of the copied one. These pointers quickly become dangling when the original object is deleted. This quickly leads to crashes. The solution is to update the Adapters pointers when performing a move. The copy constructor isn't useful for format objects and can thus be deleted. This resolves PR33388. Differential Revision: https://reviews.llvm.org/D34463 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318333 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r315310:Tom Stellard2017-11-143-4/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r315310 | sdardis | 2017-10-10 06:34:45 -0700 (Tue, 10 Oct 2017) | 22 lines [mips] Partially fix PR34391 Previously, the parsing of the 'subu $reg, ($reg,) imm' relied on a parser which also rendered the operand to the instruction. In some cases the general parser could construct an MCExpr which was not a MCConstantExpr which MipsAsmParser was expecting. Address this by altering the special handling to cope with unexpected inputs and fine-tune the handling of cases where an register name that is not available in the current ABI is regarded as not a match for the custom parser but also not as an outright error. Also enforces the binutils restriction that only constants are accepted. This partially resolves PR34391. Thanks to Ed Maste for reporting the issue! Reviewers: nitesh.jain, arichardson Differential Revision: https://reviews.llvm.org/D37476 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318192 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r317204 and r318172:Tom Stellard2017-11-144-41/+263
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r317204 | sdardis | 2017-11-02 05:47:22 -0700 (Thu, 02 Nov 2017) | 15 lines [mips] Use register scavenging with MSA. MSA stores and loads to the stack are more likely to require an emergency GPR spill slot due to the smaller offsets available with those instructions. Handle this by overestimating the size of the stack by determining the largest offset presuming that all callee save registers are spilled and accounting of incoming arguments when determining whether an emergency spill slot is required. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39056 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r318172 | sdardis | 2017-11-14 11:11:45 -0800 (Tue, 14 Nov 2017) | 5 lines [mips] Simplify test for 5.0.1 (NFC) Simplify testing that an emergency spill slot is used when MSA is used so that it can be included in the 5.0.1 release. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318191 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r317470:Tom Stellard2017-11-142-4/+32
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r317470 | sdardis | 2017-11-06 02:50:04 -0800 (Mon, 06 Nov 2017) | 12 lines [mips] Fix PR35140 Mark all symbols involved with TLS relocations as being TLS symbols. This resolves PR35140. Thanks to Alex Crichton for reporting the issue! Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D39591 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318188 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314798:Tom Stellard2017-11-144-0/+69
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314798 | sdardis | 2017-10-03 06:45:49 -0700 (Tue, 03 Oct 2017) | 9 lines [mips] Enable spilling and reloading of the dsp register set. The dsp register class is an alias of the gpr register class, so we have to define instructions for spilling and reloading. Reviewers: atanasyan Differential Revision: https://reviews.llvm.org/D38038 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318183 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r310543:Tom Stellard2017-11-142-0/+21
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r310543 | pcc | 2017-08-09 18:07:44 -0700 (Wed, 09 Aug 2017) | 9 lines Linker: Create a function declaration when moving a non-prevailing alias of function type. We were previously creating a global variable of function type, which is invalid IR. This issue was exposed by r304690, in which we started asserting that global variables were of a valid type. Fixes PR33462. Differential Revision: https://reviews.llvm.org/D36438 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318181 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r310522:Tom Stellard2017-11-1411-2/+176
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r310522 | belleyb | 2017-08-09 13:58:39 -0700 (Wed, 09 Aug 2017) | 8 lines [Linker] PR33527 - Linker::LinkOnlyNeeded should import AppendingLinkage globals Linker::LinkOnlyNeeded should always import globals with AppendingLinkage. This resolves PR33527. Differential Revision: https://reviews.llvm.org/D34448 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318180 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r316824:Tom Stellard2017-11-132-0/+12
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r316824 | haicheng | 2017-10-27 19:27:14 -0700 (Fri, 27 Oct 2017) | 7 lines [ConstantFold] Fix a crash when folding a GEP that has vector index LLVM crashes when factoring out an out-of-bound index into preceding dimension and the preceding dimension uses vector index. Simply bail out now when this case happens. Differential Revision: https://reviews.llvm.org/D38677 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@318096 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r315485:Tom Stellard2017-10-252-0/+70
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r315485 | spatel | 2017-10-11 11:24:21 -0700 (Wed, 11 Oct 2017) | 7 lines [x86] avoid infinite loop from SoftenFloatOperand (PR34866) Legalization of fp128 assumes things that we should have asserts for, so that's another potential improvement. Differential Revision: https://reviews.llvm.org/D38771 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@316607 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314898:Dylan McKay2017-10-141-1/+44
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314898 | dylanmckay | 2017-10-04 23:37:22 +1300 (Wed, 04 Oct 2017) | 6 lines [AVR] Implement LPMWRdZ pseudo-instruction's expansion. FIXME: implementation is mostly copy-pasted from LDWRdPtr, so we should refactor a bit and unify the two Patch by Gerdo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315836 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314897:Dylan McKay2017-10-141-2/+2
| | | | | | | | | | | | | ------------------------------------------------------------------------ r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines [AVR] Factor out mayLoad in tablegen patterns Patch by Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315835 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314896:Dylan McKay2017-10-148-33/+33
| | | | | | | | | | | | | ------------------------------------------------------------------------ r314896 | dylanmckay | 2017-10-04 23:33:36 +1300 (Wed, 04 Oct 2017) | 3 lines [AVR] Elaborate LDWRdPtr into `ld r, X++; ld r+1, X` Patch by Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315834 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314891:Dylan McKay2017-10-143-2/+4159
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314891 | dylanmckay | 2017-10-04 22:51:28 +1300 (Wed, 04 Oct 2017) | 8 lines [AVR] Insert JMP for long branches Previously, on long branches (relative jumps of >4 kB), an assertion failure was hit, as AVRInstrInfo::insertIndirectBranch was not implemented. Despite its name, it is called by the branch relaxator for *all* unconditional jumps. Patch by Thomas Backman. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315833 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314890:Dylan McKay2017-10-143-5/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314890 | dylanmckay | 2017-10-04 22:51:21 +1300 (Wed, 04 Oct 2017) | 16 lines [AVR] Fix displacement overflow for LDDW/STDW In some cases, the code generator attempts to generate instructions such as: lddw r24, Y+63 which expands to: ldd r24, Y+63 ldd r25, Y+64 # Oops! This is actually ld r25, Y in the binary This commit limits the first offset to 62, and thus the second to 63. It also updates some asserts in AVRExpandPseudoInsts.cpp, including for INW and OUTW, which appear to be unused. Patch by Thomas Backman. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315832 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312357:Tom Stellard2017-10-132-0/+34
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312357 | davide | 2017-09-01 12:54:08 -0700 (Fri, 01 Sep 2017) | 9 lines [TTI] Fix getGEPCost() for geps with a single operand. Previously this would sporadically crash as TargetType was never initialized. We special-case the single-operand case returning earlier and trying to mimic the behaviour of isLegalAddressingMode as closely as possible. Differential Revision: https://reviews.llvm.org/D37277 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315663 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r313366:Craig Topper2017-10-082-0/+75
| | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r313366 | ctopper | 2017-09-15 10:09:03 -0700 (Fri, 15 Sep 2017) | 9 lines [X86] Don't create i64 constants on 32-bit targets when lowering v64i1 constant build vectors When handling a v64i1 build vector of constants on 32-bit targets we were creating an illegal i64 constant that we then bitcasted back to v64i1. We need to instead create two 32-bit constants, bitcast them to v32i1 and concat the result. We should also take care to handle the halves being all zeros/ones after the split. This patch splits the build vector and then recursively lowers the two pieces. This allows us to handle the all ones and all zeros cases with minimal effort. Ideally we'd just do the split and concat, and let lowering get called again on the new nodes, but getNode has special handling for CONCAT_VECTORS that reassembles the pieces back into a single BUILD_VECTOR. Hopefully the two temporary BUILD_VECTORS we had to create to do this that don't get returned don't cause any issues. Fixes PR34605. Differential Revision: https://reviews.llvm.org/D37858 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315198 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert r314892Dylan McKay2017-10-043-4159/+2
| | | | | | | It was accidentally merged. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314893 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314891:Dylan McKay2017-10-043-2/+4159
| | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314891 | dylanmckay | 2017-10-04 22:51:28 +1300 (Wed, 04 Oct 2017) | 8 lines [AVR] Insert JMP for long branches Previously, on long branches (relative jumps of >4 kB), an assertion failure was hit, as AVRInstrInfo::insertIndirectBranch was not implemented. Despite its name, it is called by the branch relaxator for *all* unconditional jumps. Patch by Thomas Backman. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314892 91177308-0d34-0410-b5e6-96231b3b80d8
* [release_50] Merging r313916Renato Golin2017-10-034-11/+39
| | | | | | | | | | | | | | | | | | | | | | | [AArch64] Fix bug in store of vector 0 DAGCombine. Summary: Avoid using XZR/WZR directly as operands to split stores of zero vectors. Doing so can lead to the XZR/WZR being used by an instruction that doesn't allow it (e.g. add). Fixes bug 34674. Reviewers: t.p.northover, efriedma, MatzeB Subscribers: aemerson, rengolin, javed.absar, mcrosier, eraman, llvm-commits, kristof.beyls Differential Revision: https://reviews.llvm.org/D38146 PR34695. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314796 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r311951 and r312038:Tom Stellard2017-09-292-4/+38
| | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r311951 | adrian | 2017-08-28 16:07:43 -0700 (Mon, 28 Aug 2017) | 6 lines Fix a logic error in DwarfExpression::addMachineReg() This fixes PR34323 and thus splitting undescribable registers into smaller, describable sub-registers. https://bugs.llvm.org/show_bug.cgi?id=34323 ------------------------------------------------------------------------ ------------------------------------------------------------------------ r312038 | joerg | 2017-08-29 14:18:07 -0700 (Tue, 29 Aug 2017) | 2 lines Simplify test case, so that it works for both trunk and release-5.0. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314567 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312348:Tom Stellard2017-09-295-3/+84
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312348 | matze | 2017-09-01 11:36:26 -0700 (Fri, 01 Sep 2017) | 39 lines LiveIntervalAnalysis: Fix alias regunit reserved definition A register in CodeGen can be marked as reserved: In that case we consider the register always live and do not use (or rather ignore) kill/dead/undef operand flags. LiveIntervalAnalysis however tracks liveness per register unit (not per register). We already needed adjustments for this in r292871 to deal with super/sub registers. However I did not look at aliased register there. Looking at ARM: FPSCR (regunits FPSCR, FPSCR~FPSCR_NZCV) aliases with FPSCR_NZCV (regunits FPSCR_NZCV, FPSCR~FPSCR_NZCV) hence they share a register unit (FPSCR~FPSCR_NZCV) that represents the aliased parts of the registers. This shared register unit was previously considered non-reserved, however given that we uses of the reserved FPSCR potentially violate some rules (like uses without defs) we should make FPSCR~FPSCR_NZCV reserved too and stop tracking liveness for it. This patch: - Defines a register unit as reserved when: At least for one root register, the root register and all its super registers are reserved. - Adjust LiveIntervals::computeRegUnitRange() for new reserved definition. - Add MachineRegisterInfo::isReservedRegUnit() to have a canonical way of testing. - Stop computing LiveRanges for reserved register units in HMEditor even with UpdateFlags enabled. - Skip verification of uses of reserved reg units in the machine verifier (this usually didn't happen because there would be no cached liverange but there is no guarantee for that and I would run into this case before the HMEditor tweak, so may as well fix the verifier too). Note that this should only affect ARMs FPSCR/FPSCR_NZCV registers today; aliased registers are rarely used, the only other cases are hexagons P0-P3/P3_0 and C8/USR pairs which are not mixing reserved/non-reserved registers in an alias. Differential Revision: https://reviews.llvm.org/D37356 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314565 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314252:Tom Stellard2017-09-292-3/+33
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314252 | gberry | 2017-09-26 14:40:46 -0700 (Tue, 26 Sep 2017) | 12 lines [AArch64][Falkor] Fix bug in falkor prefetcher fix pass. Summary: In rare cases, loads that don't get prefetched that were marked as strided loads could cause a crash if they occurred in a loop with other colliding loads. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38261 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314555 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314251:Tom Stellard2017-09-292-60/+318
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314251 | gberry | 2017-09-26 14:40:41 -0700 (Tue, 26 Sep 2017) | 16 lines [AArch64][Falkor] Fix correctness bug in falkor prefetcher fix pass and correct some opcode tag computations. Summary: This addresses a correctness bug for LD[1234]*_POST opcodes that have the prefetcher fix applied to them: the base register was not being written back from the temp after being incremented, so it would appear to never be incremented. Also, fix some opcode tag computations based on some updated HW details to get better tag avoidance and thus better prefetcher performance. Reviewers: mcrosier Subscribers: aemerson, rengolin, javed.absar, kristof.beyls Differential Revision: https://reviews.llvm.org/D38256 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314554 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r311599:Tom Stellard2017-09-291-1/+1
| | | | | | | | | | | | | ------------------------------------------------------------------------ r311599 | gberry | 2017-08-23 14:11:28 -0700 (Wed, 23 Aug 2017) | 4 lines [AArch64][Falkor] Fix bug in Falkor HWPF tag collision avoidance LDPDi was incorrectly marked as ignoring the destination register in the prefetcher tag. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314553 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r313998:Tom Stellard2017-09-282-0/+4
| | | | | | | | | | | | ------------------------------------------------------------------------ r313998 | bmakam | 2017-09-22 10:46:36 -0700 (Fri, 22 Sep 2017) | 3 lines [Falkor] Add falkor CPU to host detection This returns "falkor" for Falkor CPU. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314437 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r311921:Joerg Sonnenberger2017-09-2814-21/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r311921 | joerg | 2017-08-28 22:20:47 +0200 (Mon, 28 Aug 2017) | 16 lines Fix ARMv4 support ARMv4 doesn't support the "BX" instruction, which has been introduced with ARMv4t. Adjust the call lowering and tail call implementation accordingly. Further changes are necessary to ensure that presence of the v4t feature is correctly set. Most importantly, the "generic" CPU for thumb-* triples should include ARMv4t, since thumb mode without thumb support would naturally be pointless. Add a couple of asserts to ensure thumb instructions are not emitted without CPU support. Differential Revision: https://reviews.llvm.org/D37030 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314417 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314180:Dylan McKay2017-09-281-2/+4
| | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314180 | dylanmckay | 2017-09-26 13:51:03 +1300 (Tue, 26 Sep 2017) | 7 lines [AVR] When lowering shifts into loops, put newly generated MBBs in the same spot as the original MBB Discovered in avr-rust/rust#62 https://github.com/avr-rust/rust/issues/62 Patch by Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314383 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314183:Dylan McKay2017-09-283-9/+9
| | | | | | | | | | | | | ------------------------------------------------------------------------ r314183 | dylanmckay | 2017-09-26 15:07:54 +1300 (Tue, 26 Sep 2017) | 3 lines [AVR] Fix the build after setting alignment to 1 in r314179 Changing all types to be byte-aligned broke a small number of tests. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314382 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314179:Dylan McKay2017-09-281-1/+1
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314179 | dylanmckay | 2017-09-26 13:45:27 +1300 (Tue, 26 Sep 2017) | 11 lines [AVR] Use 1-byte alignment for all data types This was an oversight in the original backend data layout. The AVR architecture does not have the concept of unaligned loads - all loads/stores from all addresses are aligned to one byte. Discovered in avr-rust issue #64 https://github.com/avr-rust/rust/issues/64 Patch By Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314379 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r311620:Dylan McKay2017-09-272-22/+65
| | | | | | | | | | | ------------------------------------------------------------------------ r311620 | dylanmckay | 2017-08-24 12:14:38 +1200 (Thu, 24 Aug 2017) | 1 line [AVR] Use the correct register classes for 16-bit atomic operations ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314358 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r314070:Dylan McKay2017-09-271-0/+5
| | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r314070 | dylanmckay | 2017-09-24 14:07:26 +1300 (Sun, 24 Sep 2017) | 6 lines [AVR] Implement getCmpLibcallReturnType(). This fixes the avr-rust issue (#75) with floating-point comparisons generating broken code. By default, LLVM assumes these comparisons return 32-bit values, but ours are 8-bit. Patch By Thomas Backman. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314357 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312905:Dylan McKay2017-09-274-0/+32
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312905 | dylanmckay | 2017-09-11 22:32:51 +1200 (Mon, 11 Sep 2017) | 10 lines [AVR] Enable the '__do_copy_data' function Also enables '__do_clear_bss'. These functions are automaticalled called by the CRT if they are declared. We need these to be called otherwise RAM will start completely uninitialised, even though we need to copy RAM variables from progmem to RAM. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314356 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312337:Tom Stellard2017-09-272-4/+40
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states Summary: This fixes a bug that was exposed on gfx9 in various GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests, e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36193 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314327 91177308-0d34-0410-b5e6-96231b3b80d8
* Revert "Merging r312337:"Tom Stellard2017-09-272-40/+4
| | | | | | | | | This reverts commit r314324. I unintentionally deleted most of the svn:mergeinfo for the release_50 branch with this commit. git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314326 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312337:Tom Stellard2017-09-272-4/+40
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312337 | nha | 2017-09-01 09:56:32 -0700 (Fri, 01 Sep 2017) | 12 lines AMDGPU: IMPLICIT_DEFs and DBG_VALUEs do not contribute to wait states Summary: This fixes a bug that was exposed on gfx9 in various GL45-CTS.shaders.loops.*_iterations.select_iteration_count_fragment tests, e.g. GL45-CTS.shaders.loops.do_while_uniform_iterations.select_iteration_count_fragment Reviewers: arsenm Subscribers: kzhuravl, wdng, yaxunl, dstuttard, tpr, t-tye, llvm-commits Differential Revision: https://reviews.llvm.org/D36193 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@314324 91177308-0d34-0410-b5e6-96231b3b80d8
* Bump version to 5.0.1Tom Stellard2017-09-151-1/+1
| | | | git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@313339 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r313334:Tom Stellard2017-09-151-40/+50
| | | | | | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r313334 | tstellar | 2017-09-14 19:25:22 -0700 (Thu, 14 Sep 2017) | 15 lines merge-request.sh: Update to use new "Fixed by Commit(s)" field Summary: This will be used instead of the url field to track which commits need to be merged. This patch also drops support for version 1.x of the bugzilla CLI tool. Reviewers: hansw, hans Reviewed By: hans Subscribers: hans, llvm-commits Differential Revision: https://reviews.llvm.org/D37786 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@313337 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312285:Hans Wennborg2017-09-011-22/+45
| | | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312285 | ctopper | 2017-08-31 14:39:23 -0700 (Thu, 31 Aug 2017) | 11 lines [X86] Don't pull carry through X86ISD::ADD carryin, -1 if we can't guranteed we're really using the carry flag from the add. Prior to this patch we had a DAG combine that tried to bypass an X86ISD::ADD with -1 being added to the carry flag of some previous operation. We would then pass the carry flag directly to user. But this is only safe if the user is looking for the carry flag and not the zero flag. So we need to only do this combine in a context where we know what flag the consumer is using. Fixes PR34381. Differential Revision: https://reviews.llvm.org/D37317 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@312333 91177308-0d34-0410-b5e6-96231b3b80d8
* Merging r312022:Hans Wennborg2017-08-292-6/+21
| | | | | | | | | | | | | | | | | | | | ------------------------------------------------------------------------ r312022 | hans | 2017-08-29 11:41:00 -0700 (Tue, 29 Aug 2017) | 10 lines [DAG] Bound loop dependence check in merge optimization. The loop dependence check looks for dependencies between store merge candidates not captured by the chain sub-DAG doing a check of predecessors which may be very large. Conservatively bound number of nodes checked for compilation time. (Resolves PR34326). Landing on behalf of Nirav Dave to unblock the 5.0.0 release. Differential Revision: https://reviews.llvm.org/D37220 ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@312041 91177308-0d34-0410-b5e6-96231b3b80d8
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