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* Rebase and use RISCVVtype helpersupstream/users/wangpc-pp/spr/clangriscv-add-assumptions-to-vsetvlivsetvlimaxwangpc2024-03-0611881-644033/+819761
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| * [AArch64] Fix fptoi/itofp for bf16David Majnemer2024-03-066-74/+672
| * [nfc] Fix RTTI for `InstrProf` intrinsics (#83511)Mircea Trofin2024-03-051-2/+35
| * Convert many LivePhysRegs uses to LiveRegUnits (#83905)AtariDreams2024-03-0612-104/+96
| * [RISCV] Use uint32_t for NumOfVReg in getVLENFactoredAmount. (#84110)Craig Topper2024-03-051-4/+4
| * [clangd] Show argument names for function pointer struct fields (#69011)Qwinci2024-03-052-0/+23
| * [mlir][complex] Support fast math flag in converting complex.atan2 op (#82101)Kai Sasaki2024-03-062-10/+582
| * [clangd] Remove calls to getFileLoc() in declToSym() (#83532)Nathan Ridge2024-03-052-3/+10
| * [clangd] Make all calls to format::getStyle() go through getFormatStyleForFil...Nathan Ridge2024-03-055-27/+19
| * AMDGPU: Correct cycle counts for f64 mfma on gfx940 (#83782)Matt Arsenault2024-03-064-36/+79
| * [libc] Fix standalone cross compiling build for the GPU (#84042)Joseph Huber2024-03-052-4/+24
| * [CUDA] Correctly set CUDA default architecture (#84017)Joseph Huber2024-03-057-124/+123
| * [WebAssembly] Use RefTypeMem2Local instead of Mem2Reg (#83196)Heejin Ahn2024-03-054-12/+9
| * [RISCV] Add TargetParser to MCA (#84109)Wang Pengcheng2024-03-061-0/+1
| * [libomptarget] Fix libomptarget.rtl.amdgpu.so installationYe Luo2024-03-051-1/+0
| * [gn build] Port 85388a06b602LLVM GN Syncbot2024-03-062-1/+1
| * Revert "[mlir][py] better support for arith.constant construction" (#84103)Mehdi Amini2024-03-052-59/+2
| * [RISCV] Move RISCVVType namespace to TargetParser (#83222)Wang Pengcheng2024-03-068-165/+173
| * AMDGPU: Define and Use HasInterpInsts for interp inst definitions (#84102)Changpeng Fang2024-03-053-2/+9
| * [InstrProf][NFC] Fix -Wimplicit-fallthrough warning in InstrProf.cpp after #8...wanglei2024-03-061-1/+0
| * [lldb] Fix build failure in Debugger.cpp (NFC)Jie Fu2024-03-061-1/+1
| * [SCEV] Migrate a couple tests to be auto generatedPhilip Reames2024-03-052-71/+221
| * [Clang][LoongArch] Fix wrong return value type of __iocsrrd_h (#84100)wanglei2024-03-063-9/+9
| * Rename llvm::ThreadPool -> llvm::DefaultThreadPool (NFC) (#83702)Mehdi Amini2024-03-0537-66/+65
| * [SCEV] Migrate some tests to be autogeneratedPhilip Reames2024-03-0514-149/+434
| * [TTI] Add alignment argument to TTI for compress/expand support (#83516)Kolya Panchenko2024-03-056-21/+31
| * [clang-tidy] fix false negative in cppcoreguidelines-missing-std-forward (#83...Qizhi Hu2024-03-063-5/+18
| * [Clang][LoongArch] Precommit test for fix wrong return value type of __iocsrr...wanglei2024-03-062-10/+40
| * [RISCV] Improve error message when the extension is not supported (#83989)Brandon Wu2024-03-063-12/+33
| * [RISCV][SiFive] Add RISCVUsage for SiFive Intelligence Extensions (#84010)Brandon Wu2024-03-061-0/+9
| * [clang][RISCV] Reorder sema check for RVV type (#83553)Brandon Wu2024-03-062-7/+7
| * [RISCV] Don't remove extends for i1 indices in mgather/mscatter (#83951)Luke Lau2024-03-063-4/+36
| * [X86][AVX512BF16] Add a few missing insert/extract patternsBenjamin Kramer2024-03-062-0/+33
| * Revert "[AArch64] Verify ldp/stp alignment stricter" (#84096)Florian Mayer2024-03-052-81/+19
| * AMDGPU: Define HasExpOrExportInsts for export instruction definitions. (#84083)Changpeng Fang2024-03-054-3/+12
| * [ORC][MachO] Simplify use of LC_BUILD_VERSION in JITDylib headers.Lang Hames2024-03-053-1/+51
| * [RISCV] Always use signed APSInt in getExactInteger. (#84070)Craig Topper2024-03-052-7/+8
| * [InstCombine] Fix shift calculation in InstCombineCasts (#84027)Quentin Dian2024-03-062-2/+17
| * [BOLT] Add reading support for Linux kernel .parainstructions section (#83965)Maksim Panchenko2024-03-052-0/+138
| * [AArch64] Implement -fno-plt for SelectionDAG/GlobalISelFangrui Song2024-03-059-68/+116
| * AMDGPU: Copy SubtargetPredicate from pseudo for DSDIR_Real (#84057)Changpeng Fang2024-03-051-0/+3
| * [flang] Added lowering and runtime for COMPLEX(16) intrinsics. (#83874)Slava Zakharin2024-03-0534-233/+444
| * [HLSL] implement the rcp intrinsic (#83857)Farzon Lotfi2024-03-057-7/+144
| * [RISCV] Add test for incorrect FP build vector lowering. NFCCraig Topper2024-03-051-0/+17
| * [SPIR-V] Memory leak fix in SPIRVEmitIntrinsics (#83015)bwlodarcz2024-03-051-121/+152
| * [compiler-rt/darwin] Disable building sanitizers on platforms without fork()....rohit-rao2024-03-051-1/+1
| * [OpenACC] Fix typo in StmtOpenACC.cpp header.erichkeane2024-03-051-1/+1
| * Use the new ThreadPoolInterface base class instead of the concrete implementa...Mehdi Amini2024-03-056-10/+10
| * [SystemZ] [z/OS] Emit offset to PPA2 in separate MCSection (#84043)Neumann Hon2024-03-053-0/+10
| * [libc++abi] Always re-export std:: exception types from libc++abi (#84031)Louis Dionne2024-03-051-1/+4
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