From 87bc8d750582f39c40896ecd8809c4f66c5bab04 Mon Sep 17 00:00:00 2001 From: Dylan McKay Date: Sat, 14 Oct 2017 22:30:44 +0000 Subject: Merging r314897: ------------------------------------------------------------------------ r314897 | dylanmckay | 2017-10-04 23:36:07 +1300 (Wed, 04 Oct 2017) | 3 lines [AVR] Factor out mayLoad in tablegen patterns Patch by Gergo Erdi. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_50@315835 91177308-0d34-0410-b5e6-96231b3b80d8 --- lib/Target/AVR/AVRInstrInfo.td | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/lib/Target/AVR/AVRInstrInfo.td b/lib/Target/AVR/AVRInstrInfo.td index 8c7b6f243928..7d1bfc8d85e0 100644 --- a/lib/Target/AVR/AVRInstrInfo.td +++ b/lib/Target/AVR/AVRInstrInfo.td @@ -1417,6 +1417,7 @@ def STDWPtrQRr : Pseudo<(outs), // Load program memory operations. let canFoldAsLoad = 1, isReMaterializable = 1, +mayLoad = 1, hasSideEffects = 0 in { let Defs = [R0], @@ -1437,8 +1438,7 @@ hasSideEffects = 0 in Requires<[HasLPMX]>; // Load program memory, while postincrementing the Z register. - let mayLoad = 1, - Defs = [R31R30] in + let Defs = [R31R30] in { def LPMRdZPi : FLPMX<0, 1, -- cgit v1.2.3