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| author | Denis Shienkov <denis.shienkov@gmail.com> | 2020-05-14 18:17:34 +0300 |
|---|---|---|
| committer | Denis Shienkov <denis.shienkov@gmail.com> | 2020-05-15 11:24:36 +0000 |
| commit | 0b4b2baa5967b7d212688bc8d723977d795c96d8 (patch) | |
| tree | c4360bb7cc8ecb58798b49397e5dbdfb46c245e1 /doc | |
| parent | 1783034f5dd98c1d4d34589e7eba5f3de8af3153 (diff) | |
doc: Add mention about new supported RISC-V architecture
Change-Id: I4b20ff0fb005b49d7444eacf429dc19210d2200d
Reviewed-by: Christian Kandeler <christian.kandeler@qt.io>
Diffstat (limited to 'doc')
| -rw-r--r-- | doc/reference/modules/qbs-module.qdoc | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/doc/reference/modules/qbs-module.qdoc b/doc/reference/modules/qbs-module.qdoc index 3acdcd484..d88b1a852 100644 --- a/doc/reference/modules/qbs-module.qdoc +++ b/doc/reference/modules/qbs-module.qdoc @@ -358,6 +358,10 @@ \li 32-bit automotive microcontroller family manufactured by Renesas Electronics \row + \li \c{"riscv"} + \li Open and free standard instruction set architecture based on established + RISC principles + \row \li \c{"rl78"} \li 16- and 8-bit accumulator-based register-bank CISC architecture with 3-stage instruction pipelining microcontroller family manufactured |