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authorGustavo Romero <gromero@linux.vnet.ibm.com>2017-07-20 17:49:02 -0400
committerMark Wielaard <mark@klomp.org>2017-07-25 12:20:42 +0200
commit55a471f5fe44945414af243613d4590c4e7cd8d1 (patch)
tree54e51962b2d00e9bb61a7fc3123f15a7fefb58fa /backends
parent55cb7dfa7e9afb3660b21e51434641c7287baf11 (diff)
ppc64: Add HTM SPRs support to readelf
Since POWER8, PowerPC 64 supports Hardware Transactional Memory, which has three special purpose registers associated to it: tfhar, tfiar, and texasr. This commit add HTM SPRs set as known note type so it's possible to use 'readelf --notes' to inspect the HTM SPRs in a coredump file generated in such a machines. Signed-off-by: Gustavo Romero <gromero@linux.vnet.ibm.com>
Diffstat (limited to 'backends')
-rw-r--r--backends/ChangeLog8
-rw-r--r--backends/ppc_corenote.c13
-rw-r--r--backends/ppc_regs.c10
3 files changed, 28 insertions, 3 deletions
diff --git a/backends/ChangeLog b/backends/ChangeLog
index 88b9764a..83710c19 100644
--- a/backends/ChangeLog
+++ b/backends/ChangeLog
@@ -1,4 +1,10 @@
-2017-08-20 Mark Wielaard <mark@klomp.org>
+2017-07-19 Gustavo Romero <gromero@linux.vnet.ibm.com>
+
+ * ppc_corenote.c: Add offsets for ppc64 HTM SPRs: thfar, tfiar,
+ and texasr.
+ * ppc_regs.c: Add names for ppc64 HTM SPRs mappings.
+
+2017-07-20 Mark Wielaard <mark@klomp.org>
* aarch64_init.c (aarch64_init): Hook data_marker_symbol.
* aarch64_symbol.c (aarch64_data_marker_symbol): New function.
diff --git a/backends/ppc_corenote.c b/backends/ppc_corenote.c
index 9ac88712..2b4ada7a 100644
--- a/backends/ppc_corenote.c
+++ b/backends/ppc_corenote.c
@@ -94,9 +94,20 @@ static const Ebl_Register_Location spe_regs[] =
{ .offset = 34 * 4, .regno = 612, .count = 1, .bits = 32 }
};
+static const Ebl_Register_Location tm_spr_regs[] =
+ {
+ /* tfhar */
+ { .offset = 0, .regno = 114, .count = 1, .bits = 64 },
+ /* texasr */
+ { .offset = 8, .regno = 116, .count = 1, .bits = 64 },
+ /* tfiar */
+ { .offset = 16, .regno = 115, .count = 1, .bits = 64 }
+ };
+
#define EXTRA_NOTES \
EXTRA_REGSET (NT_PPC_VMX, 34 * 16, altivec_regs) \
- EXTRA_REGSET (NT_PPC_SPE, 35 * 4, spe_regs)
+ EXTRA_REGSET (NT_PPC_SPE, 35 * 4, spe_regs) \
+ EXTRA_REGSET (NT_PPC_TM_SPR, 3 * 8, tm_spr_regs)
#if BITS == 32
# define ULONG uint32_t
diff --git a/backends/ppc_regs.c b/backends/ppc_regs.c
index bcf4f7a3..c2d50118 100644
--- a/backends/ppc_regs.c
+++ b/backends/ppc_regs.c
@@ -149,7 +149,15 @@ ppc_register_info (Ebl *ebl __attribute__ ((unused)),
namelen = 4;
break;
- case 110 ... 117:
+ case 114:
+ return stpcpy (name, "tfhar") + 1 - name;
+ case 115:
+ return stpcpy (name, "tfiar") + 1 - name;
+ case 116:
+ return stpcpy (name, "texasr") + 1 - name;
+
+ case 110 ... 113:
+ case 117:
case 120 ... 121:
case 123 ... 199:
name[0] = 's';