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-rw-r--r--src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h119
1 files changed, 59 insertions, 60 deletions
diff --git a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h
index f7e2fb4767..078de44748 100644
--- a/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h
+++ b/src/3rdparty/javascriptcore/JavaScriptCore/assembler/ARMv7Assembler.h
@@ -28,7 +28,7 @@
#include <wtf/Platform.h>
-#if ENABLE(ASSEMBLER) && PLATFORM_ARM_ARCH(7)
+#if ENABLE(ASSEMBLER) && PLATFORM(ARM_THUMB2)
#include "AssemblerBuffer.h"
#include <wtf/Assertions.h>
@@ -37,7 +37,7 @@
namespace JSC {
-namespace ARM {
+namespace ARMRegisters {
typedef enum {
r0,
r1,
@@ -199,7 +199,7 @@ class ARMThumbImmediate {
};
} PatternBytes;
- ALWAYS_INLINE static int32_t countLeadingZerosPartial(uint32_t& value, int32_t& zeros, const int N)
+ ALWAYS_INLINE static void countLeadingZerosPartial(uint32_t& value, int32_t& zeros, const int N)
{
if (value & ~((1<<N)-1)) /* check for any of the top N bits (of 2N bits) are set */ \
value >>= N; /* if any were set, lose the bottom N */ \
@@ -407,8 +407,8 @@ register writeback
class ARMv7Assembler {
public:
- typedef ARM::RegisterID RegisterID;
- typedef ARM::FPRegisterID FPRegisterID;
+ typedef ARMRegisters::RegisterID RegisterID;
+ typedef ARMRegisters::FPRegisterID FPRegisterID;
// (HS, LO, HI, LS) -> (AE, B, A, BE)
// (VS, VC) -> (O, NO)
@@ -442,7 +442,6 @@ public:
{
}
- void enableLatePatch() { }
private:
JmpSrc(int offset)
: m_offset(offset)
@@ -481,7 +480,7 @@ private:
// ARMv7, Appx-A.6.3
bool BadReg(RegisterID reg)
{
- return (reg == ARM::sp) || (reg == ARM::pc);
+ return (reg == ARMRegisters::sp) || (reg == ARMRegisters::pc);
}
bool isSingleRegister(FPRegisterID reg)
@@ -693,16 +692,16 @@ public:
void add(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)
{
// Rd can only be SP if Rn is also SP.
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isValid());
- if (rn == ARM::sp) {
+ if (rn == ARMRegisters::sp) {
if (!(rd & 8) && imm.isUInt10()) {
m_formatter.oneWordOp5Reg3Imm8(OP_ADD_SP_imm_T1, rd, imm.getUInt10() >> 2);
return;
- } else if ((rd == ARM::sp) && imm.isUInt9()) {
+ } else if ((rd == ARMRegisters::sp) && imm.isUInt9()) {
m_formatter.oneWordOp9Imm7(OP_ADD_SP_imm_T2, imm.getUInt9() >> 2);
return;
}
@@ -726,9 +725,9 @@ public:
void add(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
{
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
m_formatter.twoWordOp12Reg4FourFours(OP_ADD_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
}
@@ -750,9 +749,9 @@ public:
void add_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)
{
// Rd can only be SP if Rn is also SP.
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isEncodedImm());
if (!((rd | rn) & 8)) {
@@ -771,9 +770,9 @@ public:
// Not allowed in an IT (if then) block?
void add_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
{
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
m_formatter.twoWordOp12Reg4FourFours(OP_ADD_S_reg_T3, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
}
@@ -839,7 +838,7 @@ public:
// Only allowed in IT (if then) block if last instruction.
JmpSrc blx(RegisterID rm)
{
- ASSERT(rm != ARM::pc);
+ ASSERT(rm != ARMRegisters::pc);
m_formatter.oneWordOp8RegReg143(OP_BLX, rm, (RegisterID)8);
return JmpSrc(m_formatter.size());
}
@@ -858,7 +857,7 @@ public:
void cmn(RegisterID rn, ARMThumbImmediate imm)
{
- ASSERT(rn != ARM::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isEncodedImm());
m_formatter.twoWordOp5i6Imm4Reg4EncodedImm(OP_CMN_imm, rn, (RegisterID)0xf, imm);
@@ -866,7 +865,7 @@ public:
void cmp(RegisterID rn, ARMThumbImmediate imm)
{
- ASSERT(rn != ARM::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isEncodedImm());
if (!(rn & 8) && imm.isUInt8())
@@ -877,7 +876,7 @@ public:
void cmp(RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
{
- ASSERT(rn != ARM::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
m_formatter.twoWordOp12Reg4FourFours(OP_CMP_reg_T2, rn, FourFours(shift.hi4(), 0xf, shift.lo4(), rm));
}
@@ -939,15 +938,15 @@ public:
m_formatter.oneWordOp8Imm8(OP_IT, ifThenElse(cond, inst2if, inst3if, inst4if));
}
- // rt == ARM::pc only allowed if last instruction in IT (if then) block.
+ // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
void ldr(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
{
- ASSERT(rn != ARM::pc); // LDR (literal)
+ ASSERT(rn != ARMRegisters::pc); // LDR (literal)
ASSERT(imm.isUInt12());
if (!((rt | rn) & 8) && imm.isUInt7())
m_formatter.oneWordOp5Imm5Reg3Reg3(OP_LDR_imm_T1, imm.getUInt7() >> 2, rn, rt);
- else if ((rn == ARM::sp) && !(rt & 8) && imm.isUInt10())
+ else if ((rn == ARMRegisters::sp) && !(rt & 8) && imm.isUInt10())
m_formatter.oneWordOp5Reg3Imm8(OP_LDR_imm_T2, rt, imm.getUInt10() >> 2);
else
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDR_imm_T3, rn, rt, imm.getUInt12());
@@ -966,8 +965,8 @@ public:
// if (wback) REG[rn] = _tmp
void ldr(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
{
- ASSERT(rt != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT(rt != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(index || wback);
ASSERT(!wback | (rt != rn));
@@ -986,10 +985,10 @@ public:
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_LDR_imm_T4, rn, rt, offset);
}
- // rt == ARM::pc only allowed if last instruction in IT (if then) block.
+ // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
void ldr(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)
{
- ASSERT(rn != ARM::pc); // LDR (literal)
+ ASSERT(rn != ARMRegisters::pc); // LDR (literal)
ASSERT(!BadReg(rm));
ASSERT(shift <= 3);
@@ -999,10 +998,10 @@ public:
m_formatter.twoWordOp12Reg4FourFours(OP_LDR_reg_T2, rn, FourFours(rt, 0, shift, rm));
}
- // rt == ARM::pc only allowed if last instruction in IT (if then) block.
+ // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
void ldrh(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
{
- ASSERT(rn != ARM::pc); // LDR (literal)
+ ASSERT(rn != ARMRegisters::pc); // LDR (literal)
ASSERT(imm.isUInt12());
if (!((rt | rn) & 8) && imm.isUInt6())
@@ -1024,8 +1023,8 @@ public:
// if (wback) REG[rn] = _tmp
void ldrh(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
{
- ASSERT(rt != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT(rt != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(index || wback);
ASSERT(!wback | (rt != rn));
@@ -1047,7 +1046,7 @@ public:
void ldrh(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)
{
ASSERT(!BadReg(rt)); // Memory hint
- ASSERT(rn != ARM::pc); // LDRH (literal)
+ ASSERT(rn != ARMRegisters::pc); // LDRH (literal)
ASSERT(!BadReg(rm));
ASSERT(shift <= 3);
@@ -1198,16 +1197,16 @@ public:
m_formatter.twoWordOp12Reg4FourFours(OP_SMULL_T1, rn, FourFours(rdLo, rdHi, 0, rm));
}
- // rt == ARM::pc only allowed if last instruction in IT (if then) block.
+ // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
void str(RegisterID rt, RegisterID rn, ARMThumbImmediate imm)
{
- ASSERT(rt != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT(rt != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isUInt12());
if (!((rt | rn) & 8) && imm.isUInt7())
m_formatter.oneWordOp5Imm5Reg3Reg3(OP_STR_imm_T1, imm.getUInt7() >> 2, rn, rt);
- else if ((rn == ARM::sp) && !(rt & 8) && imm.isUInt10())
+ else if ((rn == ARMRegisters::sp) && !(rt & 8) && imm.isUInt10())
m_formatter.oneWordOp5Reg3Imm8(OP_STR_imm_T2, rt, imm.getUInt10() >> 2);
else
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_STR_imm_T3, rn, rt, imm.getUInt12());
@@ -1226,8 +1225,8 @@ public:
// if (wback) REG[rn] = _tmp
void str(RegisterID rt, RegisterID rn, int offset, bool index, bool wback)
{
- ASSERT(rt != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT(rt != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(index || wback);
ASSERT(!wback | (rt != rn));
@@ -1246,10 +1245,10 @@ public:
m_formatter.twoWordOp12Reg4Reg4Imm12(OP_STR_imm_T4, rn, rt, offset);
}
- // rt == ARM::pc only allowed if last instruction in IT (if then) block.
+ // rt == ARMRegisters::pc only allowed if last instruction in IT (if then) block.
void str(RegisterID rt, RegisterID rn, RegisterID rm, unsigned shift=0)
{
- ASSERT(rn != ARM::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
ASSERT(shift <= 3);
@@ -1262,12 +1261,12 @@ public:
void sub(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)
{
// Rd can only be SP if Rn is also SP.
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isValid());
- if ((rn == ARM::sp) && (rd == ARM::sp) && imm.isUInt9()) {
+ if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) {
m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2);
return;
} else if (!((rd | rn) & 8)) {
@@ -1290,9 +1289,9 @@ public:
void sub(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
{
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
m_formatter.twoWordOp12Reg4FourFours(OP_SUB_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
}
@@ -1310,12 +1309,12 @@ public:
void sub_S(RegisterID rd, RegisterID rn, ARMThumbImmediate imm)
{
// Rd can only be SP if Rn is also SP.
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(imm.isValid());
- if ((rn == ARM::sp) && (rd == ARM::sp) && imm.isUInt9()) {
+ if ((rn == ARMRegisters::sp) && (rd == ARMRegisters::sp) && imm.isUInt9()) {
m_formatter.oneWordOp9Imm7(OP_SUB_SP_imm_T1, imm.getUInt9() >> 2);
return;
} else if (!((rd | rn) & 8)) {
@@ -1334,9 +1333,9 @@ public:
// Not allowed in an IT (if then) block?
void sub_S(RegisterID rd, RegisterID rn, RegisterID rm, ShiftTypeAndAmount shift)
{
- ASSERT((rd != ARM::sp) || (rn == ARM::sp));
- ASSERT(rd != ARM::pc);
- ASSERT(rn != ARM::pc);
+ ASSERT((rd != ARMRegisters::sp) || (rn == ARMRegisters::sp));
+ ASSERT(rd != ARMRegisters::pc);
+ ASSERT(rn != ARMRegisters::pc);
ASSERT(!BadReg(rm));
m_formatter.twoWordOp12Reg4FourFours(OP_SUB_S_reg_T2, rn, FourFours(shift.hi4(), rd, shift.lo4(), rm));
}
@@ -1754,6 +1753,6 @@ private:
} // namespace JSC
-#endif // ENABLE(ASSEMBLER) && PLATFORM_ARM_ARCH(7)
+#endif // ENABLE(ASSEMBLER) && PLATFORM(ARM_THUMB2)
#endif // ARMAssembler_h
generated by cgit v1.2.3 (git 2.25.1) at 2024-06-11 17:10:23 +0000