diff options
author | Thiago Macieira <thiago.macieira@intel.com> | 2012-06-12 14:44:24 +0200 |
---|---|---|
committer | Qt by Nokia <qt-info@nokia.com> | 2012-06-12 17:35:06 +0200 |
commit | 53546ce0b6ac033bb3c8c26fcdc886c824f09184 (patch) | |
tree | ac433d14e4039816bb9eda67017195cc9dfa4eaa /config.tests/arch | |
parent | b4525b34074665ed472cd421077a1633110f16a7 (diff) |
Update listing of when SSSE3 and SSE4.1 first became available
SSSE3 was first available on the original Intel Core 2 processors, so
add the "Merom" codename. SSE4.1 was available on the 45 nm shrink of
those processors, codename "Penryn", not on the next architecture.
Change-Id: I5fd92db62aa409b7f4e46f9b24d960519177f811
Reviewed-by: Giuseppe D'Angelo <giuseppe.dangelo@kdab.com>
Diffstat (limited to 'config.tests/arch')
-rw-r--r-- | config.tests/arch/arch.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp index da0fe1c1b7..e9530e63c6 100644 --- a/config.tests/arch/arch.cpp +++ b/config.tests/arch/arch.cpp @@ -182,7 +182,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" " sse3" #endif #ifdef __SSSE3__ -// Supplemental SSE3, Intel Core 2, AMD "Bulldozer" +// Supplemental SSE3, Intel Core 2 ("Merom"), AMD "Bulldozer" " ssse3" #endif #ifdef __SSE4A__ @@ -190,7 +190,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" " sse4a" #endif #ifdef __SSE4_1__ -// SSE 4.1, Intel Core-i7 ("Nehalem"), AMD "Bulldozer" +// SSE 4.1, Intel Core2 45nm shrink ("Penryn"), AMD "Bulldozer" " sse4.1" #endif #ifdef __SSE4_2__ |