diff options
| author | Thiago Macieira <thiago.macieira@intel.com> | 2013-08-06 16:24:57 -0700 |
|---|---|---|
| committer | The Qt Project <gerrit-noreply@qt-project.org> | 2013-08-22 02:04:39 +0200 |
| commit | 04bc63f2d642d2144757ef1ab5e65b5518d534f5 (patch) | |
| tree | c008ea5ab899fb8e6f79323eb898aba84af3f8cd /config.tests/arch | |
| parent | 065cff83119a58973d1e00434ade1d26012a09d5 (diff) | |
Add x86 arch detection support for AVX512 and SHA instructions
The flags come from GCC commit 201219:
http://gcc.gnu.org/viewcvs/gcc/branches/avx512/gcc/config/i386/i386-c.c?limit_changes=0&r1=201219&r2=201218&pathrev=201219
Clang and ICC don't seem to have support for this yet.
Change-Id: Ic941654a5c56ed110d0e754e436a92dc5deaeb17
Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@digia.com>
Diffstat (limited to 'config.tests/arch')
| -rw-r--r-- | config.tests/arch/arch.cpp | 20 |
1 files changed, 20 insertions, 0 deletions
diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp index b9c244e29e..b3c0d3b7d2 100644 --- a/config.tests/arch/arch.cpp +++ b/config.tests/arch/arch.cpp @@ -106,6 +106,22 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // AVX 2, Intel Core 4th Generation ("Haswell") " avx2" #endif +#ifdef __AVX512F__ +// AVX512 Foundation, Intel Xeon Phi codename "Knights Landing" +" avx512f" +#endif +#ifdef __AVX512CD__ +// AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing" +" avx512cd" +#endif +#ifdef __AVX512ER__ +// AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing" +" avx512ef" +#endif +#ifdef __AVX512PF__ +// AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing" +" avx512pf" +#endif #ifdef __BMI__ // Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2" " bmi" @@ -169,6 +185,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // Random number generator, Intel Core 3rd Generation ("Ivy Bridge") " rdrnd" #endif +#ifdef __SHA__ +// SHA-1 and SHA-256 instructions, Intel processor TBA +" sha" +#endif #if defined(__SSE__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1) || defined(_M_X64) // Streaming SIMD Extensions, Intel Pentium III, AMD Athlon " sse" |