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| author | Thiago Macieira <thiago.macieira@intel.com> | 2014-07-30 09:53:01 -0700 |
|---|---|---|
| committer | Thiago Macieira <thiago.macieira@intel.com> | 2014-07-31 00:52:37 +0200 |
| commit | 84f5d4b756049ec80d8f206d87d870d98ec6525a (patch) | |
| tree | 66fe5da1fa012e53badd6410e7c11d42c3911c9d /config.tests | |
| parent | 01cce1282015b791834999e5ce96fed8faa63c98 (diff) | |
Add the detection of the compiler macros for more AVX512 features
Change-Id: I1d1f2c3857824b17185bc47398299ea7f92c5568
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Diffstat (limited to 'config.tests')
| -rw-r--r-- | config.tests/arch/arch.cpp | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp index a5718c1d90..35bf2be91c 100644 --- a/config.tests/arch/arch.cpp +++ b/config.tests/arch/arch.cpp @@ -85,6 +85,14 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing" " avx512cd" #endif +#ifdef __AVX512DQ__ +// AVX512 Double & Quadword, future Intel Xeon processor +" avx512dq" +#endif +#ifdef __AVX512BW__ +// AVX512 Byte & Word, future Intel Xeon processor +" avx512bw" +#endif #ifdef __AVX512ER__ // AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing" " avx512ef" @@ -93,6 +101,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing" " avx512pf" #endif +#ifdef __AVX512VL__ +// AVX512 Vector Length, future Intel Xeon processor +" avx512vl" +#endif #ifdef __BMI__ // Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2" " bmi" |