diff options
| author | Thiago Macieira <thiago.macieira@intel.com> | 2017-01-27 13:09:55 -0800 |
|---|---|---|
| committer | Thiago Macieira <thiago.macieira@intel.com> | 2017-02-21 23:48:30 +0000 |
| commit | 0f1b6acab7713b05223f029bf9201daf42096d3b (patch) | |
| tree | 1f905bf9b7a86c411e41ea17918a26e4e0d9fc3b /mkspecs/features/simd.prf | |
| parent | db1c8553a189af5b2574ce38f2ac83bbf23464b6 (diff) | |
x86: Add detection of the AES and SHA New Instructions
The AES instructions were first introduced with the Westmere shrink
(22nm) of the Nehalem architecture. The SHA instructions are still
pending on Intel architecture, but is available on AMD family 17h (gcc
argument -march=znver1).
Both features operate on SSE registers, so that's why the MSVC command-
line argument is the SSE2 one and the configure-time tests depend on
features.sse2.
The qmake feature names end in "ni" because "aes" and "sha" are too
simple and could clash with other uses. The QT_COMPILER_SUPPORTS_ macro
doesn't have the "NI" suffix because it has to match the GCC/Clang
predefined macro.
Change-Id: I445bb15619f6401494e8fffd149dbd1f862ff51c
Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
Diffstat (limited to 'mkspecs/features/simd.prf')
| -rw-r--r-- | mkspecs/features/simd.prf | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/mkspecs/features/simd.prf b/mkspecs/features/simd.prf index 953fc52c65..aca9ae6243 100644 --- a/mkspecs/features/simd.prf +++ b/mkspecs/features/simd.prf @@ -93,6 +93,8 @@ addSimdCompiler(sse3) addSimdCompiler(ssse3) addSimdCompiler(sse4_1) addSimdCompiler(sse4_2) +addSimdCompiler(aesni) +addSimdCompiler(shani) addSimdCompiler(avx) addSimdCompiler(avx2) addSimdCompiler(avx512f) |