diff options
| author | Thiago Macieira <thiago@kde.org> | 2011-07-31 19:14:42 -0300 |
|---|---|---|
| committer | Qt by Nokia <qt-info@nokia.com> | 2012-01-24 01:08:42 +0100 |
| commit | 1955353149781a064bc053b86be6e221b159d4ee (patch) | |
| tree | 459d78d98b80cee79ef150a831454d70b288f5ba /src/corelib/thread | |
| parent | 99fb1bea49c4de5cf3143af59f8c96a92980e58f (diff) | |
Port the IA-64 atomics to the new QBasicAtomicXXX architecture
The IA-64 architecture supports the actual memory ordering semantics
in many instructions, but not all. We actually implement the functions
for all operations, so we get the best possible output.
It does support proper load-acquire and store-release semantics, but
we don't need instructions for it: the ABI requires that a volatile
load be acquire and a volatile store be release.
The Intel and HP compiler codepaths are rewritten, but untested.
Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
Diffstat (limited to 'src/corelib/thread')
| -rw-r--r-- | src/corelib/thread/qbasicatomic.h | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/corelib/thread/qbasicatomic.h b/src/corelib/thread/qbasicatomic.h index 89192a5e91..a39ed0d56a 100644 --- a/src/corelib/thread/qbasicatomic.h +++ b/src/corelib/thread/qbasicatomic.h @@ -52,6 +52,8 @@ # include <QtCore/qatomic_arm.h> #elif defined(__i386) || defined(__i386__) # include <QtCore/qatomic_i386.h> +#elif defined(__ia64) || defined(__ia64__) +# include "QtCore/qatomic_ia64.h" #elif defined(__mips) || defined(__mips__) # include "QtCore/qatomic_mips.h" #elif defined(__x86_64) || defined(__x86_64__) || defined(__amd64) |