1 files changed, 14 insertions, 37 deletions
diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp
index e08183c193..35bf2be91c 100644
--- a/config.tests/arch/arch.cpp
+++ b/config.tests/arch/arch.cpp
@@ -41,46 +41,11 @@
 ****************************************************************************/
 
 #define QGLOBAL_H
-#include "../../src/corelib/global/qprocessordetection.h"
+#include "../../src/corelib/global/archdetect.cpp"
 #include <stdio.h>
 
 extern const char msg[];
-const char msg[] = "==Qt=magic=Qt== Architecture:"
-
-#if defined(Q_PROCESSOR_ALPHA)
-"alpha"
-#elif defined(Q_PROCESSOR_ARM)
-"arm"
-#elif defined(Q_PROCESSOR_AVR32)
-"avr32"
-#elif defined(Q_PROCESSOR_BLACKFIN)
-"bfin"
-#elif defined(Q_PROCESSOR_X86_32)
-"i386"
-#elif defined(Q_PROCESSOR_X86_64)
-"x86_64"
-#elif defined(Q_PROCESSOR_IA64)
-"ia64"
-#elif defined(Q_PROCESSOR_MIPS_64)
-"mips64"
-#elif defined(Q_PROCESSOR_MIPS)
-"mips"
-#elif defined(Q_PROCESSOR_POWER)
-"power"
-#elif defined(Q_PROCESSOR_S390_X)
-"s390x"
-#elif defined(Q_PROCESSOR_S390)
-"s390"
-#elif defined(Q_PROCESSOR_SH)
-"sh"
-#elif defined(Q_PROCESSORS_SPARC_64)
-"sparc64"
-#elif defined(Q_PROCESSOR_SPARC)
-"sparc"
-#else
-"unknown"
-#endif
-                   ;
+const char msg[] = "==Qt=magic=Qt== Architecture:" ARCH_PROCESSOR;
 
 extern const char msg2[];
 const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
@@ -120,6 +85,14 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
 // AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing"
 " avx512cd"
 #endif
+#ifdef __AVX512DQ__
+// AVX512 Double & Quadword, future Intel Xeon processor
+" avx512dq"
+#endif
+#ifdef __AVX512BW__
+// AVX512 Byte & Word, future Intel Xeon processor
+" avx512bw"
+#endif
 #ifdef __AVX512ER__
 // AVX512 Exponentiation & Reciprocal, Intel Xeon Phi codename "Knights Landing"
 " avx512ef"
@@ -128,6 +101,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:"
 // AVX512 Prefetch, Intel Xeon Phi codename "Knights Landing"
 " avx512pf"
 #endif
+#ifdef __AVX512VL__
+// AVX512 Vector Length, future Intel Xeon processor
+" avx512vl"
+#endif
 #ifdef __BMI__
 // Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2"
 " bmi"