diff options
Diffstat (limited to 'config.tests/arch/arch.cpp')
| -rw-r--r-- | config.tests/arch/arch.cpp | 44 |
1 files changed, 38 insertions, 6 deletions
diff --git a/config.tests/arch/arch.cpp b/config.tests/arch/arch.cpp index bb3efec177..2ccfe127b5 100644 --- a/config.tests/arch/arch.cpp +++ b/config.tests/arch/arch.cpp @@ -80,19 +80,19 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" " avx2" #endif #ifdef __AVX512F__ -// AVX512 Foundation, Intel Xeon Phi codename "Knights Landing" and Intel Xeon codename "Skylake" +// AVX512 Foundation, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake") " avx512f" #endif #ifdef __AVX512CD__ -// AVX512 Conflict Detection, Intel Xeon Phi codename "Knights Landing" and Intel Xeon codename "Skylake" +// AVX512 Conflict Detection, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake") " avx512cd" #endif #ifdef __AVX512DQ__ -// AVX512 Double & Quadword, Intel Xeon processor codename "Skylake" +// AVX512 Double & Quadword, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake") " avx512dq" #endif #ifdef __AVX512BW__ -// AVX512 Byte & Word, Intel Xeon processor codename "Skylake" +// AVX512 Byte & Word, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake") " avx512bw" #endif #ifdef __AVX512ER__ @@ -104,7 +104,7 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" " avx512pf" #endif #ifdef __AVX512VL__ -// AVX512 Vector Length, Intel Xeon processor codename "Skylake" +// AVX512 Vector Length, Intel Xeon Scalable ("Skylake" server), some Intel Core 7th generation ("Skylake") " avx512vl" #endif #ifdef __AVX512IFMA__ @@ -115,6 +115,22 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // AVX512 Vector Byte Manipulation Instructions, Intel processor codename "Cannonlake" " avx512vbmi" #endif +#ifdef __AVX512VBMI2__ +// AVX512 Vector Byte Manipulation Instructions #2, Intel processor codename "Ice Lake" +" avx512vbmi2" +#endif +#ifdef __AVX512VPOPCNTDQ__ +// AVX512 Vector Population Count Double & Quad, Future Intel Xeon Phi processor codename "Knights Mill", Intel processor codename "Ice Lake" +" avx512vpopcntdq" +#endif +#ifdef __AVX5124FMAPS__ +// AVX512 4-iteration Fused Multiply Accumulation Packed Single, Future Intel Xeon Phi processor codename "Knights Mill" +" avx5124fmaps" +#endif +#ifdef __AVX5124VNNIW__ +// AVX512 4-iteration Vector Neural Network Instructions Word, Future Intel Xeon Phi processor codename "Knights Mill" +" avx5124vnniw" +#endif #ifdef __BMI__ // Bit Manipulation Instructions 1, Intel Core 4th Generation ("Haswell"), AMD "Bulldozer 2" " bmi" @@ -145,6 +161,14 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // rdfsgsbase, wrfsgsbase, Intel Core 3rd Generation ("Ivy Bridge") " fsgsbase" #endif +#ifdef __GFNI__ +// Galois Field new instructions, Intel processor codename "Ice Lake" +" gfni" +#endif +#ifdef __IBT__ +// Indirect Branch Tracking, Intel processor TBA +" ibt" +#endif #ifdef __LWP__ // LWP instructions, AMD "Bulldozer" " lwp" @@ -186,6 +210,10 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" // Prefetch data for writing, Intel Core 5th Generation ("Broadwell") " prfchw" #endif +#ifdef __RDPID__ +// Read Processor ID, Intel processors codename "Ice Lake" and "Goldmont Plus" +" rdpid" +#endif #ifdef __RDRND__ // Random number generator, Intel Core 3rd Generation ("Ivy Bridge") " rdrnd" @@ -199,9 +227,13 @@ const char msg2[] = "==Qt=magic=Qt== Sub-architecture:" " rtm" #endif #ifdef __SHA__ -// SHA-1 and SHA-256 instructions, Intel processor TBA +// SHA-1 and SHA-256 instructions, Intel processors codename "Cannon Lake" and "Goldmont" " sha" #endif +#ifdef __SHSTK__ +// Shadow stack, Intel processor TBA +" shstk" +#endif #if defined(__SSE__) || (defined(_M_IX86_FP) && _M_IX86_FP >= 1) || defined(_M_X64) // Streaming SIMD Extensions, Intel Pentium III, AMD Athlon " sse" |