diff options
Diffstat (limited to 'src/corelib/global/qsimd_p.h')
| -rw-r--r-- | src/corelib/global/qsimd_p.h | 19 |
1 files changed, 13 insertions, 6 deletions
diff --git a/src/corelib/global/qsimd_p.h b/src/corelib/global/qsimd_p.h index 1feedbbb23..64ba527d2c 100644 --- a/src/corelib/global/qsimd_p.h +++ b/src/corelib/global/qsimd_p.h @@ -206,14 +206,15 @@ asm( // The Intel Core 4th generation was codenamed "Haswell" and introduced AVX2, // BMI1, BMI2, FMA, LZCNT, MOVBE, which makes it a good divider for a // sub-target for us. The first AMD processor with AVX2 support (Zen) has the -// same features. This feature set was chosen as the version 3 of the x86-64 -// ISA (x86-64-v3) and is supported by GCC and Clang. +// same features, but had already introduced BMI1 in the previous generation. +// This feature set was chosen as the version 3 of the x86-64 ISA (x86-64-v3) +// and is supported by GCC and Clang. // // macOS's fat binaries support the "x86_64h" sub-architecture and the GNU libc // ELF loader also supports a "haswell/" subdir (e.g., /usr/lib/haswell). -# define ARCH_HASWELL_MACROS (__AVX2__ + __BMI__ + __BMI2__ + __F16C__ + __FMA__ + __LZCNT__) +# define ARCH_HASWELL_MACROS (__AVX2__ + __FMA__) # if ARCH_HASWELL_MACROS != 0 -# if ARCH_HASWELL_MACROS != 6 +# if ARCH_HASWELL_MACROS != 2 # error "Please enable all x86-64-v3 extensions; you probably want to use -march=haswell or -march=x86-64-v3 instead of -mavx2" # endif static_assert(ARCH_HASWELL_MACROS, "Undeclared identifiers indicate which features are missing."); @@ -223,8 +224,10 @@ static_assert(ARCH_HASWELL_MACROS, "Undeclared identifiers indicate which featur // x86-64 sub-architecture version 4 // -// Similar to the above, x86-64-v4 marches the AVX512 variant of the Intel Core -// 6th generation (codename "Skylake"). +// Similar to the above, x86-64-v4 matches the AVX512 variant of the Intel Core +// 6th generation (codename "Skylake"). AMD Zen4 is the their first processor +// with AVX512 support and it includes all of these too. +// # define ARCH_SKX_MACROS (__AVX512F__ + __AVX512BW__ + __AVX512CD__ + __AVX512DQ__ + __AVX512VL__) # if ARCH_SKX_MACROS != 0 # if ARCH_SKX_MACROS != 5 @@ -346,12 +349,16 @@ Q_CORE_EXPORT uint64_t QT_MANGLE_NAMESPACE(qDetectCpuFeatures)(); static inline uint64_t qCpuFeatures() { +#ifdef QT_BOOTSTRAPPED + return qCompilerCpuFeatures; // no detection +#else quint64 features = atomic_load_explicit(QT_MANGLE_NAMESPACE(qt_cpu_features), memory_order_relaxed); if (!QT_SUPPORTS_INIT_PRIORITY) { if (Q_UNLIKELY(features == 0)) features = QT_MANGLE_NAMESPACE(qDetectCpuFeatures)(); } return features; +#endif } #define qCpuHasFeature(feature) (((qCompilerCpuFeatures & CpuFeature ## feature) == CpuFeature ## feature) \ |