path: root/config.tests/avx512
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* AVX512 test: an intrinsic that GCC forgot to implement prior to GCC8Thiago Macieira2018-09-151-0/+5
| | | | | | | | | | | _mm512_mask_cvtepi32_storeu_epi8 is VPMOVDB (convert from 32-bit to 8-bit with truncation) where the destination is a memory address, with an OpMask register used to indicate which of the lanes in the vector to store. Similarly, _mm512_mask_cvtepi16_storeu_epi8 is VPMOVWB (convert from 16-bit o 8-bit), which is useful for UTF-16 to Latin1 conversion. Change-Id: I8f261579aad648fdb4f0fffd15542ea306841ce6 Reviewed-by: Allan Sandfeld Jensen <>
* Add support for AVX-512 intrinsics found in MSVC 2017 15.3Thiago Macieira2017-11-302-14/+17
| | | | | | | | | | | | | | | | | | It seems the compiler supports /arch:AVX512 and /arch:AVX512F but none of the other switches (and neither are documented). And when you pass those, you also get Conflict Detection (CD), Double & Quad (DQ), Byte & Word (BW) and Vector Length (VL), which matches the ICC switch "-xCORE-AVX512". Unlike ICC, there doesn't seem to be an option to enable only the common part of AVX-512. Support for Intel Xeon Phi's current features (Exponential & Reciprocation and Prefetch) and future ones (IFMA, VBMI, 4FMAPS, 4VNNI and VPOPCNTDQ) seems to be missing altogether. See Change-Id: I98105cd9616b8097957db680d73eb1f86e487e6d Reviewed-by: Oswald Buddenhagen <>
* configure: un-namespace remaining non-inline configure testsOswald Buddenhagen2017-08-022-0/+113
only few tests remain, and many of these were mis-classified anyway. Change-Id: Ic3bc96928a0c79fe77b9ec10e6508d4822f18df2 Reviewed-by: Thiago Macieira <>