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* Remove src/corelib/arch/nacl/* and qatomic_nacl.hBradley T. Hughes2012-02-031-2/+0
| | | | | | | | | | This implementation uses the GCC __sync_* intrinsics, which we do not need to duplicate after commit 2bbd2262b3974fb4e39341a23e40ffdf1655ebe9 (which added qatomic_gcc.h). Change-Id: I59b6e4a03e83f58f4145a5ab2bfd635fe9ab686f Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove src/corelib/arch/avr32/* and qatomic_avr32.hBradley T. Hughes2012-02-031-2/+0
| | | | | | | | | This implementation uses the GCC __sync_* intrinsics, which we do not need to duplicate after commit 2bbd2262b3974fb4e39341a23e40ffdf1655ebe9 (which added qatomic_gcc.h). Change-Id: I2cab86deacad1c37f17f0c5836d9faf2ad366495 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove #include "qatomic_macosx.h"Bradley T. Hughes2012-02-031-2/+0
| | | | | | | This file was removed in commit 68e5fd9ebc8a3f510e3144e981a0cb358945fb9c Change-Id: I76671f79432204c28ffa7488871d0eef07cc8dca Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Rename qatomic_windows.h to qatomic_msvc.hBradley T. Hughes2012-02-031-4/+0
| | | | | | | | | | The QT_ARCH_WINDOWS(CE) define(s) aren't used to control which header to include anymore, so just remove it. We also do not need the empty src/corelib/arch/windows/arch.pri. Change-Id: I5400fc852af31907e533d0278540b8cd3da391cb Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Remove "All rights reserved" line from license headers.Jason McDonald2012-01-301-1/+1
| | | | | | | | | | As in the past, to avoid rewriting various autotests that contain line-number information, an extra blank line has been inserted at the end of the license text to ensure that this commit does not change the total number of lines in the license header. Change-Id: I311e001373776812699d6efc045b5f742890c689 Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
* Port the IA-64 atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-241-2/+0
| | | | | | | | | | | | | | | | The IA-64 architecture supports the actual memory ordering semantics in many instructions, but not all. We actually implement the functions for all operations, so we get the best possible output. It does support proper load-acquire and store-release semantics, but we don't need instructions for it: the ABI requires that a volatile load be acquire and a volatile store be release. The Intel and HP compiler codepaths are rewritten, but untested. Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the MIPS atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-241-2/+0
| | | | | | | | | | | | | | | The LL/SC instructions are only present on MIPS II and up, so don't pretend to support MIPS I. The previous implementation emitted the instructions by telling the assembler to change instruction sets. Now, the user must pass an -march= option to GCC telling it which architecture or processor is being targetted. On MIPS64, the 64-bit implementation allows supporting for long long too. Change-Id: I6dae6f8f61e563aba6a663227d91c5ddf554aa6a Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the ARM atomics to the new QBasicAtomicXXX architectureThiago Macieira2012-01-241-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The implementation is divided in two files, as it used to be in the previous implementation: one for ARMv5, one for ARMv6 and up. For the ARMv5 implementation: Drop the non-Linux EABI version of the atomics, as it's not ABI-compatible with the ARMv6 and ARMv7 implementations. This means this ARMv5 implementation only works on Linux. If other systems implement kernel helpers like Linux, they can be added too. We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the operations, except for fetchAndStore, for which we use the SWP instruction. Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the memory barrier. Now this code is SMP-safe even when built with ARMv5. The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas the dmb helper was introduced in 2.6.15. That means 2.6.15 is the minimum version now. For ARMv6 and up: Introduce byte, half-word and doubleword atomics that work on ARMv6K and up. For ARMv6 specifically, the memory barrier instruction (DMB) isn't present, so we need to accomplish the same with the MCR coprocessor instruction. Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Port the i386 and x86-64 atomics to the new QBasicAtomic architectureThiago Macieira2012-01-241-4/+0
| | | | | | | | | | | | | | Both implementations now are very similar to one another, to the point we could share the code if we wanted to. They are based on assembly code for the Relaxed functions only, as the i386 and x86-64 architectures only allow for full memory ordering or something that closely resembles it (see 8.2 "Memory ordering" in the Intel 64 and IA-32 Architectures Software Developer's Manual Volume 3A). We could add "lfence/mfence/sfence" in future versions if we wanted to (SSE2+). Change-Id: I76966d9f8694edfece2c5ebd3387348fac721447 Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Update contact information in license headers.Jason McDonald2012-01-231-1/+1
| | | | | | | Replace Nokia contact email address with Qt Project website. Change-Id: I431bbbf76d7c27d8b502f87947675c116994c415 Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
* Add atomic implementation for Native Client.Morten Johan Sorvig2012-01-201-1/+1
| | | | | | | Uses gcc compiler intrinsics, similar to avr32. Change-Id: I10cc2bd3cad67ee002386bab1ea764a4ff5ce727 Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com>
* Update copyright year in license headers.Jason McDonald2012-01-051-1/+1
| | | | | Change-Id: I02f2c620296fcd91d4967d58767ea33fc4e1e7dc Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
* Remove S60/symbian specific code in corelib/archLiang Qi2011-11-011-2/+0
| | | | | | | | | Clean up and remove Symbian specific code and data. Change-Id: I41794085fd5122310b1fdf4c524c6e77d22e8500 Reviewed-by: Lars Knoll <lars.knoll@nokia.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Update licenseheader text in source files for qtbase Qt moduleJyri Tahtela2011-05-241-17/+17
| | | | | | | Updated version of LGPL and FDL licenseheaders. Apply release phase licenseheaders for all source files. Reviewed-by: Trust Me
* Initial import from the monolithic Qt.Qt by Nokia2011-04-271-0/+101
This is the beginning of revision history for this module. If you want to look at revision history older than this, please refer to the Qt Git wiki for how to use Git history grafting. At the time of writing, this wiki is located here: http://qt.gitorious.org/qt/pages/GitIntroductionWithQt If you have already performed the grafting and you don't see any history beyond this commit, try running "git log" with the "--follow" argument. Branched from the monolithic repo, Qt master branch, at commit 896db169ea224deb96c59ce8af800d019de63f12
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