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Change-Id: I9abdc674bcfa7bb38ce27c5213c5a672f59e63d5
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
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The IA-64 architecture supports the actual memory ordering semantics
in many instructions, but not all. We actually implement the functions
for all operations, so we get the best possible output.
It does support proper load-acquire and store-release semantics, but
we don't need instructions for it: the ABI requires that a volatile
load be acquire and a volatile store be release.
The Intel and HP compiler codepaths are rewritten, but untested.
Change-Id: I7aa62a4ec65f63a97d1bbd8418bb2492c2be465f
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The LL/SC instructions are only present on MIPS II and up, so don't
pretend to support MIPS I. The previous implementation emitted the
instructions by telling the assembler to change instruction sets. Now,
the user must pass an -march= option to GCC telling it which
architecture or processor is being targetted.
On MIPS64, the 64-bit implementation allows supporting for long long
too.
Change-Id: I6dae6f8f61e563aba6a663227d91c5ddf554aa6a
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The implementation is divided in two files, as it used to be in the
previous implementation: one for ARMv5, one for ARMv6 and up.
For the ARMv5 implementation:
Drop the non-Linux EABI version of the atomics, as it's not
ABI-compatible with the ARMv6 and ARMv7 implementations. This
means this ARMv5 implementation only works on Linux. If other
systems implement kernel helpers like Linux, they can be added
too.
We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the
operations, except for fetchAndStore, for which we use the SWP
instruction.
Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the
memory barrier. Now this code is SMP-safe even when built with
ARMv5.
The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas
the dmb helper was introduced in 2.6.15. That means 2.6.15 is the
minimum version now.
For ARMv6 and up:
Introduce byte, half-word and doubleword atomics that work on
ARMv6K and up.
For ARMv6 specifically, the memory barrier instruction (DMB) isn't
present, so we need to accomplish the same with the MCR
coprocessor instruction.
Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The input type needs to match the output type, otherwise we get this
error:
src/corelib/arch/qatomic_x86_64.h:288:25: error: unsupported inline asm:
input with type '<dependent type>' matching output with type 'T':
"0" (valueToAdd * QAtomicAdditiveType<T>::AddScale)
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Change-Id: I26d4efdbcab089dea71ef08e3e65df5b7482865a
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Both implementations now are very similar to one another, to the point
we could share the code if we wanted to. They are based on assembly
code for the Relaxed functions only, as the i386 and x86-64
architectures only allow for full memory ordering or something that
closely resembles it (see 8.2 "Memory ordering" in the Intel 64 and
IA-32 Architectures Software Developer's Manual Volume 3A). We could
add "lfence/mfence/sfence" in future versions if we wanted to (SSE2+).
Change-Id: I76966d9f8694edfece2c5ebd3387348fac721447
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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The code is now much simpler and much more complete. Now the bootstrap
atomics (which aren't atomic at all) contain the full set of
operations.
The only integer supported is int, but all others would work too.
Change-Id: Id99f07818f9da059c4ff02520f9cbf2d1a71a514
Reviewed-by: Bradley T. Hughes <bradley.hughes@nokia.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Replace Nokia contact email address with Qt Project website.
Change-Id: I431bbbf76d7c27d8b502f87947675c116994c415
Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
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Uses gcc compiler intrinsics, similar to avr32.
Change-Id: I10cc2bd3cad67ee002386bab1ea764a4ff5ce727
Reviewed-by: Morten Johan Sørvig <morten.sorvig@nokia.com>
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Change-Id: I02f2c620296fcd91d4967d58767ea33fc4e1e7dc
Reviewed-by: Rohan McGovern <rohan.mcgovern@nokia.com>
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Change-Id: I2301ea3fa399bcc5d6d8c6b487a3fb78db19c67a
Reviewed-by: Friedemann Kleint <Friedemann.Kleint@nokia.com>
Reviewed-by: Olivier Goffart <ogoffart@woboq.com>
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Clean up and remove Symbian specific code and
data.
Change-Id: I41794085fd5122310b1fdf4c524c6e77d22e8500
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
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Task-number: QTBUG-16402
Rubber-stamped-by: Thiago Macieira
(cherry picked from commit 6be1b235f7db38146f7080a4bfcfe3051ae54699)
Change-Id: I6f60f1d3079395e765a183961db5c8543cf58cdc
Reviewed-on: http://codereview.qt.nokia.com/3078
Reviewed-by: Qt Sanity Bot <qt_sanity_bot@ovi.com>
Reviewed-by: Eckhart Koppen <eckhart.koppen@nokia.com>
Reviewed-by: Lars Knoll <lars.knoll@nokia.com>
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(required for the metatype changes)
Change-Id: I0e3c73e7828493b4f03ec6439ec80b1c8c2bf377
Reviewed-on: http://codereview.qt.nokia.com/2105
Reviewed-by: Qt Sanity Bot <qt_sanity_bot@ovi.com>
Reviewed-by: Jędrzej Nowacki <jedrzej.nowacki@nokia.com>
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Updated version of LGPL and FDL licenseheaders.
Apply release phase licenseheaders for all source files.
Reviewed-by: Trust Me
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This is the beginning of revision history for this module. If you
want to look at revision history older than this, please refer to the
Qt Git wiki for how to use Git history grafting. At the time of
writing, this wiki is located here:
http://qt.gitorious.org/qt/pages/GitIntroductionWithQt
If you have already performed the grafting and you don't see any
history beyond this commit, try running "git log" with the "--follow"
argument.
Branched from the monolithic repo, Qt master branch, at commit
896db169ea224deb96c59ce8af800d019de63f12
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