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* SIMD: Add a haswell sub-architecture selection to our supportThiago Macieira2018-07-091-1/+42
| | | | | | | | | | | | | | | | | As the comment says, Haswell is a nice divider and is a good optimization target. I'm using -march=core-avx2 instead of -march=haswell because the latter form was only added to GCC 4.9 but we still support 4.7 and that has support for AVX2. This commit changes the AVX2-optimized code in QtGui to Haswell- optimized instead. That means, for example, that qdrawhelper_avx2.cpp can now use the FMA instructions. Change-Id: If025d476890745368955fffd153129c1716ba006 Reviewed-by: Lars Knoll <lars.knoll@qt.io> Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* SIMD: Refactor the constants to be actual bit valuesThiago Macieira2018-06-251-11/+11
| | | | | | | | | | | | ... instead of being the bit numbers. This allows us to test more than one feature at a time with qCpuHasFeature (see commit about the Haswell architecture features). The drawback is that we won't be able to handle more than 63 different CPU features, though we're likely quite far from it (x86 currently has only 36 features). Change-Id: Iff4151c519c144d580c4fffd153a0acbfd74c2c6 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* SIMD: Move the #include for qsimd_x86_p.h a bit lower in qsimd_p.hThiago Macieira2018-06-251-1/+2
| | | | | | | | | It needs to be after our extra #defines for CPU features, otherwise the qCompilerCpuFeatures variable won't be set correctly. Change-Id: Iff4151c519c144d580c4fffd153a0a93ca01bbe6 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Revert "qsimd: remove support for systems without 64-bit atomics"Thiago Macieira2018-06-071-7/+10
| | | | | | | | | | This reverts commit 6e1190053d28877b2e90375056735429525e2ee7. We had to bring back qatomic_msvc.h for MSVC 2015, which does not provide 64-bit atomics on 32-bit platforms. Task-number: QTBUG-68719 Change-Id: Iea902cf0b01191717e0a640944771fcede7b5ff8 Reviewed-by: Liang Qi <liang.qi@qt.io>
* qsimd: add support for new x86 CPU featuresThiago Macieira2018-05-051-141/+3
| | | | | | | | | | | | | | | | | | | | | | | | | This adds detection for: VAES, GFNI, AVX512VBMI2, AVX512VNNI, AVX512BITALG, AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS. These features were found in the "Intel® Architecture Instruction Set Extensions and Future Features" manual, revision 30. This commit also adds support for RDPID (already in the main manual) and the Control-flow Enforcement Technology, which appears in a separate Intel paper. This new support was done by adding a new generator script so we don't have to maintain two tables in sync, one in qsimd.cpp with the feature names, and the other in qsimd_p.h. Since we now need a lot more bits, it's no longer worth keeping the two halves of the qt_cpu_features variable mostly similar to the main two CPUID results. This commit goes back to keeping things in order, like we used to prior to commit 6a8251a89b6a61258498f4af1ba7b3d5b7f7096c (Qt 5.6) At the time of this commit, GCC 8 has macros for AVX512VPOPCNTDQ, AVX512_4NNIW, AVX512_4FMAPS, AVX512VBMI2 and GFNI. Change-Id: I938b024e38bf4aac9154fffd14f7afae50faaa96 Reviewed-by: Edward Welbourne <edward.welbourne@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* qsimd: remove support for systems without 64-bit atomicsThiago Macieira2018-05-051-10/+7
| | | | | | | | We had that as a concession for early toolchains that failed to include the necessary libraries. They must now be up-to-date. Change-Id: I938b024e38bf4aac9154fffd14f7a630ef160cd5 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Fix the enabling of AES with ICC and MSVC on some low-end processorsThiago Macieira2018-05-041-3/+2
| | | | | | | | | | | | | | GCC and Clang assume that all Sandybridge (2nd generation) and newer Intel Core™ processors have AES, which I used as a source of information for this code. However, there are a few low-end parts that miss this feature, like Intel Core™ i3-2350M, i3-3130M, i3-4000M. [1] https://ark.intel.com/products/series/75025/4th-Generation-Intel-Core-i3-Processors Task-number: QTBUG-67705 Change-Id: If90a92b041d3442fa0a4fffd1525b9afbcb6e524 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* qsimd_p.h: Reorganize and simplify the x86 intrinsics #includesThiago Macieira2018-01-251-68/+28
| | | | | | | | All of our compilers support #include <immintrin.h>, so we don't need the legacy code that includes the earlier versions. Change-Id: I938b024e38bf4aac9154fffd14f80214d1d744c8 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* Add a configure-time check for QT_COMPILER_SUPPORTS_SIMD_ALWAYSThiago Macieira2017-11-301-5/+1
| | | | | | | | | | | | | | | | This has two main benefits: 1) introduces a qmake CONFIG we can use in .pro/.pri/.prf files 2) removes the need to keep an up-to-date list of which compilers support the feature The test is implemented as trying to compile every single SIMD test we currently have, but without passing the -mXXX option. The reason for trying all of them is that some people may have modified their mkspecs to add -mXXX options or -march=XXX, which could enable the particular feature we tried, resulting in a false positive outcome. Change-Id: I938b024e38bf4aac9154fffd14f7784dc8d1f020 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io>
* Make qsimd_p.h compile in C mode tooThiago Macieira2017-11-141-4/+7
| | | | | | | | | Since we very often need to write our intrinsic-using code in C to avoid "leakage" of not-inlined inline functions, this file is very handy. Change-Id: I57a1bd6e0c194530b732fffd14f45d27a32538f8 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io>
* Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-08-311-0/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: examples/examples.pro qmake/library/qmakebuiltins.cpp src/corelib/global/qglobal.cpp Re-apply b525ec2 to qrandom.cpp(code movement in 030782e) src/corelib/global/qnamespace.qdoc src/corelib/global/qrandom.cpp src/gui/kernel/qwindow.cpp Re-apply a3d59c7 to QWindowPrivate::setVisible() (code movement in d7a9e08) src/network/ssl/qsslkey_openssl.cpp src/plugins/platforms/android/androidjniinput.cpp src/plugins/platforms/xcb/qxcbconnection.cpp src/plugins/platforms/xcb/qxcbconnection_xi2.cpp src/widgets/widgets/qmenu.cpp tests/auto/widgets/kernel/qwidget_window/tst_qwidget_window.cpp Change-Id: If7ab427804408877a93cbe02079fca58e568bfd3
| * Fix error attribute(target("+crc")) is unknownPeter Seiderer2017-08-291-0/+3
| | | | | | | | | | | | Task-number: QTBUG-61975 Change-Id: I0b1b55c0737dad485b5ace8e6eb7cb842589453d Reviewed-by: Laszlo Agocs <laszlo.agocs@qt.io>
* | Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-06-191-3/+3
|\| | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/corelib/io/qprocess_unix.cpp src/corelib/io/qprocess_win.cpp src/plugins/platforms/android/qandroidplatformintegration.h src/plugins/platforms/windows/qwindowscontext.cpp src/plugins/platforms/windows/windows.pri src/tools/uic/cpp/cppwriteinitialization.cpp src/widgets/doc/src/widgets-and-layouts/gallery.qdoc Change-Id: I8d0834c77f350ea7540140c2c7f372814afc2d0f
| * qsimd_p.h: Don't set the __xxx__ variables with Clang and GCCThiago Macieira2017-06-121-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit 418184c2a0ad97cce12717a43f84fa6f12ece189 set some extra defines that Clang and GCC do set so that MSVC and ICC builds would properly get the features detected. But that meant we set them with Clang and GCC (technically, set them again, but to the same value so no warning was printed). Don't do that. This commit allows me to use "-march=native -mno-rdrnd" to disable the unconditional use of RDRAND instruction. That's required to valgrind any applications, as the current version (3.12) does not have support for that instruction. vex amd64->IR: unhandled instruction bytes: 0x48 0xF 0xC7 0xF0 0x48 0x8B 0x55 0xE8 0x48 0x89 vex amd64->IR: REX=1 REX.W=1 REX.R=0 REX.X=0 REX.B=0 vex amd64->IR: VEX=0 VEX.L=0 VEX.nVVVV=0x0 ESC=0F vex amd64->IR: PFX.66=0 PFX.F2=0 PFX.F3=0 ==78321== valgrind: Unrecognised instruction at address 0x4ef159c. ==78321== at 0x4EF159C: _rdrand64_step (immintrin.h:208) ==78321== by 0x4EF159C: qt_random_cpu(void*, long long) (qrandom.cpp:95) Change-Id: Ia3e896da908f42939148fffd14c6884501de4fa4 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* | Add proper detection of x86 RDRAND instructionThiago Macieira2017-06-121-5/+3
| | | | | | | | | | | | | | | | | | The instruction is "RDRAND", but the feature name, according to GCC, is RDRND, so I had to change some macros in qsimd_p.h. Change-Id: Icd0e0d4b27cb4e5eb892fffd14b5166779137e63 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* | Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-04-201-2/+3
|\| | | | | | | | | | | | | | | | | | | | | | | Conflicts: src/corelib/tools/qbytearray.h src/corelib/tools/qdatetime.h src/corelib/tools/qstring.h src/corelib/tools/qversionnumber.h src/plugins/platforms/android/qandroidplatformintegration.cpp tests/auto/corelib/tools/qhashfunctions/tst_qhashfunctions.cpp Change-Id: Iefd92a435e687a76cd593099e40d9a9620a1454d
| * Update the Clang support for SIMD code generationThiago Macieira2017-04-171-2/+3
| | | | | | | | | | | | | | | | Clang 3.8 has support for __attribute__((target(xxx))) and its SIMD headers can be included unconditionally. Change-Id: Ic15b7ff417c8412893e5fffd14b5b42b950b48d7 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
| * Enable a given SIMD feature if the compiler has enabled itThiago Macieira2017-04-061-1/+1
| | | | | | | | | | Change-Id: I09100678ff4443e6be06fffd1482c08125adc0a4 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* | x86: Add detection of the AES and SHA New InstructionsThiago Macieira2017-02-211-1/+1
|/ | | | | | | | | | | | | | | | | | | The AES instructions were first introduced with the Westmere shrink (22nm) of the Nehalem architecture. The SHA instructions are still pending on Intel architecture, but is available on AMD family 17h (gcc argument -march=znver1). Both features operate on SSE registers, so that's why the MSVC command- line argument is the SSE2 one and the configure-time tests depend on features.sse2. The qmake feature names end in "ni" because "aes" and "sha" are too simple and could clash with other uses. The QT_COMPILER_SUPPORTS_ macro doesn't have the "NI" suffix because it has to match the GCC/Clang predefined macro. Change-Id: I445bb15619f6401494e8fffd149dbd1f862ff51c Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* Update the __xxx__ macros due to MSVC and ICC not defining them allThiago Macieira2017-02-121-1/+31
| | | | | | | | And if __AES__ or __PCLMUL__ is defined, then we expect wmmintrin.h to exist. Change-Id: I445bb15619f6401494e8fffd149db77dc513e071 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* Regroup the x86 QT_FUNCTION_TARGET_STRING_xxxx macrosThiago Macieira2017-01-301-7/+7
| | | | | | | Easier to have an overview of them. Change-Id: I445bb15619f6401494e8fffd149db6dec4851f6d Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* Move the declaration of SSE3 & newer macros above their useThiago Macieira2017-01-301-14/+14
| | | | | Change-Id: I445bb15619f6401494e8fffd149db66da3405b48 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@qt.io>
* Fix MIPS DSP configurationAllan Sandfeld Jensen2017-01-271-0/+9
| | | | | | | | | The patch fixes a number of bugs in code, and removes dead logic clarifying that MIPS DSP, like ARM NEON, has no runtime detecton. Change-Id: If2f4eea68da5b2eaa80b8e9c8258206d8c1b7173 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@qt.io> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Avoid auto-vectorization of epilogues of manual vectorizationAllan Sandfeld Jensen2016-10-111-0/+3
| | | | | | | | | | Defines a structure that tells the compiler in no uncertain terms the maximum number of times a loop can be run. The reduces the size of qdrawhelper_avx2.o from 22kbytes to 11kbytes. Change-Id: Ie3d6281b04b4be3332497c15f3dfe9f185e20507 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Add AVX2 versions of the fast blending functionsAllan Sandfeld Jensen2016-09-181-0/+3
| | | | | | | | This patch adds AVX2 versions of the fast blending functions that we already have SSE2 versions of. Change-Id: Ifd1a22f7891b6208cb74929ad26095d12c5a1efb Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Make sure all private headers in Qt Core include qglobal_p.hThiago Macieira2016-06-251-1/+1
| | | | | | | | | | | | The rule was: - if the header included qglobal.h, turn that into qglobal_p.h - otherwise, insert the #include after the "We mean it" warning qglobal_p.h currently only includes qglobal.h. Change-Id: Ib056b47dde3341ef9a52ffff13ef677e471674b7 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Merge remote-tracking branch 'origin/5.7' into devLiang Qi2016-06-171-27/+1
|\ | | | | | | | | | | | | Conflicts: tests/auto/widgets/itemviews/qlistview/tst_qlistview.cpp Change-Id: If899cda251b4dc8b8a7c6764520e88ab719737cd
| * Merge remote-tracking branch 'origin/5.6.1' into 5.7.0Liang Qi2016-05-261-26/+0
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: src/corelib/tools/qsimd_p.h src/network/socket/qnativesocketengine_winrt.cpp Change-Id: I2765b671664c2a84839b2f88ba724fdf0c1fa7c6
| | * Replace qUnaligned{Load,Store} with the existing q{To,From}Unalignedv5.6.1-1v5.6.1Thiago Macieira2016-05-251-37/+0
| | | | | | | | | | | | | | | | | | | | | | | | Move the Q_ALWAYS_INLINE and forcing of __builtin_memcpy to the existing functions. Change-Id: Icaa7fb2a490246bda156ffff143c137e520eea79 Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com>
| * | Check for CRC32 properlyLaszlo Agocs2016-05-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | Just being on ARMv8 does not mean CRC32 (and arm_acle.h) is available. Task-number: QTBUG-53629 Change-Id: I104f643f2d59620e1f4d1ef814a1de71bb484e7b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
| * | Merge remote-tracking branch 'origin/5.6' into 5.7Liang Qi2016-04-131-1/+7
| |\| | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: config.tests/unix/compile.test src/android/jar/src/org/qtproject/qt5/android/QtActivityDelegate.java src/testlib/qtestcase.cpp src/testlib/qtestcase.qdoc Change-Id: Ied3c471dbc9a076c8de33d673bd557e88575609d
| | * wince: Fix intrinsics for X86 platforms when SSE2 is enabledAndreas Holzammer2016-04-111-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SSE2 can use intrinsics, which are supported by WEC2013, but for WEC7 they need to be defined. Change-Id: I261f3db4db7abcb0b59598cef9cbad404635c3ec Reviewed-by: Friedemann Kleint <Friedemann.Kleint@theqtcompany.com> Reviewed-by: Gunnar Roth <gunnar.roth@gmx.net> Reviewed-by: Kevin Funk <kevin.funk@kdab.com> Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com>
* | | Remove _bit_scan_{forward,reverse}Erik Verbruggen2016-05-311-53/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use qCountTrailingZeroBits and qCountLeadingZeroBits from qalgorithms.h instead. Also extended these versions for MSVC. The _bit_scan_* versions stem from a time before the glorious days of qalgorithms.h. A big advantage is that these functions can be used on all platforms. Change-Id: I5a1b886371520310a7fe16e617635ea335046beb Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* | | Merge remote-tracking branch 'origin/5.7' into devLiang Qi2016-04-051-1/+1
|\| | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: examples/corelib/ipc/ipc.pro src/plugins/platforms/xcb/qxcbbackingstore.cpp tests/auto/corelib/tools/qcommandlineparser/tst_qcommandlineparser.cpp Change-Id: Ia006e10ff1732fe78f90138c41f05b59b49486cf
| * | Remove the traces of the discontinued android-no-sdk platformEirik Aavitsland2016-03-301-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Cleaning out the workarounds for the discontinued "Embedded Android" platform of Boot2Qt. Change-Id: I0ff9d770e82a43457fb7e5da0428f4597ead4038 Reviewed-by: Eskil Abrahamsen Blomfeldt <eskil.abrahamsen-blomfeldt@theqtcompany.com> Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com>
* | | QtCore: Remove Windows CE.Friedemann Kleint2016-03-301-2/+2
|/ / | | | | | | | | | | | | | | | | Remove QSysInfo::WV_CE_5/6 enumeration values, #ifdef sections for Q_OS_WINCE and wince .pro file clauses in library, examples and tests. Task-number: QTBUG-51673 Change-Id: Ib63463445f3a26e04d018b193e4655030002f5f9 Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com>
* | Merge remote-tracking branch 'origin/5.6' into 5.7Liang Qi2016-03-111-0/+26
|\| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change partially reverts 1bfc7f68 about QT_HAS_BUILTIN define and undef in src/corelib/tools/qsimd_p.h. This change is also squashed with "Fall back to c++11 standard compiler flag for host builds" which is done by Peter Seiderer. Conflicts: mkspecs/features/default_post.prf src/3rdparty/sqlite/0001-Fixing-the-SQLite3-build-for-WEC2013-again.patch src/3rdparty/sqlite/sqlite3.c src/corelib/tools/qsimd_p.h src/gui/kernel/qevent.cpp src/gui/kernel/qwindowsysteminterface.cpp src/gui/kernel/qwindowsysteminterface_p.h src/plugins/bearer/blackberry/blackberry.pro src/plugins/platforms/cocoa/qcocoasystemsettings.mm src/plugins/platformthemes/gtk2/gtk2.pro src/plugins/styles/bb10style/bb10style.pro src/sql/drivers/sqlite2/qsql_sqlite2.cpp tools/configure/configureapp.cpp Task-number: QTBUG-51644 Done-with: Peter Seiderer <ps.report@gmx.net> Change-Id: I6100d6ace31b2e8d41a95f0b5d5ebf8f1fd88b44
| * QString, QJson, QHash: Fix UBs involving unaligned loadsMarc Mutz2016-03-091-0/+37
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Found by UBSan: src/corelib/tools/qstring.cpp:587:42: runtime error: load of misaligned address 0x2acbf4b7551b for type 'const long long int', which requires 8 byte alignment src/corelib/json/qjson_p.h:405:30: runtime error: store to misaligned address 0x0000019b1e52 for type 'quint64', which requires 8 byte alignment src/corelib/tools/qhash.cpp:116:27: runtime error: load of misaligned address 0x2b8f9ce80e85 for type 'const qlonglong', which requires 8 byte alignment src/corelib/tools/qhash.cpp:133:26: runtime error: load of misaligned address 0x2b8f9ce80e8d for type 'const ushort', which requires 2 byte alignment Fix by memcpy()ing into a local variable. Wrap this trick in template functions in qsimd_p.h. These are marked as always- inline and use __builtin_memcpy() where available in an attempt to avoid the memcpy() function call overhead in debug builds. While this looks prohibitively expensive, from the pov of the C++ abstract machine, it is 100% equivalent, except for the absence of undefined behavior. In one case, the cast produces a local temporary which is then copied into the function, and in the other case, that local variable comes from return value of qUnalignedLoad(). Consequently, GCC compiles these two versions into identical assembler code (only verfied for ucstrncmp, but there's no reason to believe that it wouldn't hold for the other cases, too). Task-number: QTBUG-51651 Change-Id: Ia50d4a1d7580b6f803e0895c9f3d89c7da37840c Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com> Reviewed-by: Allan Sandfeld Jensen <allan.jensen@theqtcompany.com>
* | iOS: Disable usage of crc32 intrinsics.Erik Verbruggen2016-03-081-0/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | To quote http://lists.llvm.org/pipermail/cfe-commits/Week-of-Mon-20160222/151168.html : > AArch64: fix Cyclone CPU features list. > It turns out we don't have CRC after all. Who knew? So clang did define __ARM_FEATURE_CRC32, while the CPU didn't support the crc32 instructions, resulting in EXC_BAD_INSTRUCTION. Change-Id: I4b0123ac5e7fd04696c05bfe7dacce205cffac8f Task-number: QTBUG-51168 Reviewed-by: Tor Arne Vestbø <tor.arne.vestbo@theqtcompany.com>
* | Add Intel copyright to files that Intel has had non-trivial contributionThiago Macieira2016-01-211-0/+1
| | | | | | | | | | | | | | | | | | I wrote a script to help find the files, but I reviewed the contributions manually to be sure I wasn't claiming copyright for search & replace, adding Q_DECL_NOTHROW or adding "We mean it" headers. Change-Id: I7a9e11d7b64a4cc78e24ffff142b506368fc8842 Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com>
* | Updated license headersJani Heikkinen2016-01-151-14/+20
| | | | | | | | | | | | | | | | | | | | | | From Qt 5.7 -> LGPL v2.1 isn't an option anymore, see http://blog.qt.io/blog/2016/01/13/new-agreement-with-the-kde-free-qt-foundation/ Updated license headers to use new LGPL header instead of LGPL21 one (in those files which will be under LGPL v3) Change-Id: I046ec3e47b1876cd7b4b0353a576b352e3a946d9 Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com>
* | ARMv8: add crc32 feature detection.Erik Verbruggen2016-01-131-2/+22
| | | | | | | | | | Change-Id: I3cfac90dfa137d0bf3d124d87262eb2dbb56459c Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* | Use __builtin_clz/ctz when available.Erik Verbruggen2015-12-011-1/+17
| | | | | | | | | | | | | | | | Nicely ask the compiler if it has a built-in for clz/ctz before resorting to CPU specific brute force measurements. Change-Id: Ifa992267ec4528219d7da14524af738316ceeaea Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* | Merge remote-tracking branch 'origin/5.6' into devSimon Hausmann2015-11-271-1/+5
|\| | | | | | | Change-Id: Ib43c6f126998eefcfed9a7c1f2bcbac8b4dd05ec
| * Detect NEON on AArch64Allan Sandfeld Jensen2015-11-261-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | The __ARM_NEON is the standard define for NEON instructions support __ARM_NEON__ is only legacy, and specifically not defined in AArch64 builds, which causes us not to detect NEON support there. The NEON assembler files doesn't build with AArch64, so the NEON drawhelper methods must be excluded for now. Change-Id: Ie32f855bde94ee7efd8a8ddb7766c931778e729b Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* | Merge remote-tracking branch 'origin/5.6' into devLiang Qi2015-10-141-4/+3
|\| | | | | | | | | | | | | | | | | Conflicts: tests/auto/corelib/io/qfile/tst_qfile.cpp tests/auto/corelib/io/qprocess/tst_qprocess.cpp tests/auto/corelib/tools/qversionnumber/qversionnumber.pro Change-Id: Ia93ce500349d96a2fbf0b4a37b73f088cc505c6e
| * Revert "Add support for same-file intrinsics with Clang 3.7"Thiago Macieira2015-10-011-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 39c2b8c5c12dfb8560fa04ce346a129adb223e29. The feature is not working: $ clang -c -o /dev/null -msse2 -include tmmintrin.h -xc /dev/null In file included from <built-in>:316: In file included from <command line>:1: /home/thiago/clang3.7/bin/../lib/clang/3.7.0/include/tmmintrin.h:28:2: error: "SSSE3 instruction set not enabled" For reference: $ icpc -c -o /dev/null -msse2 -include tmmintrin.h -xc /dev/null; echo $? 0 $ gcc -c -o /dev/null -msse2 -include tmmintrin.h -xc /dev/null; echo $? 0 Change-Id: I42e7ef1a481840699a8dffff140844cb8872ed6e Reviewed-by: Sérgio Martins <sergio.martins@kdab.com>
| * Fix ICC warning about use of "defined" in a macroThiago Macieira2015-09-251-1/+1
| | | | | | | | | | | | | | qhash.cpp(89): warning #3199: "defined" is always false in a macro expansion in Microsoft mode Change-Id: I7de033f80b0e4431b7f1ffff13fc960bcbb17352 Reviewed-by: Olivier Goffart (Woboq GmbH) <ogoffart@woboq.com>
* | configure: Add support for detecting AVX512 instructionsThiago Macieira2015-09-251-0/+1
|/ | | | | | | | | | | | | | | | | Tested on Linux with Clang 3.7, GCC 4.9, 5.1 and 6.0, ICC 16 beta; on OS X with Clang-XCode 6.4, ICC 16 beta; on Windows with MSVC 2013 and ICC 15. MinGW is not tested. GCC 4.9: AVX512F AVX512ER AVX512CD AVX512PF GCC 5 & 6: AVX512F AVX512ER AVX512CD AVX512PF AVX512DQ AVX512BW AVX512VL AVX512IFMA AVX512VBMI Clang 3.7: AVX512F AVX512ER AVX512CD Clang-XCode: <none> ICC 15 & 16: AVX512F AVX512ER AVX512CD AVX512PF AVX512DQ AVX512BW AVX512VL MSVC 2013: <none> Change-Id: Ib306f8f647014b399b87ffff13f1da1b161c31d7 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* Expand reporting of the Intel instruction set extensionsThiago Macieira2015-09-221-1/+92
| | | | | | | | | | | | | | | Detection for most of them is free because we're loading the entire registers anyway. The only exception is AVX512VBMI, which is in a new register we hadn't yet read from. I've also added the new GCC names so they can be used with QT_FUNCTION_TARGET. The only two exceptions are "movbe" and "popcnt", which are extremely restricted in use and we are not likely to have code dedicated to using them. Change-Id: Ib306f8f647014b399b87ffff13f1d8fd29e58be0 Reviewed-by: Oswald Buddenhagen <oswald.buddenhagen@theqtcompany.com> Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-05-01 17:13:18 +0000