From 0f1b6acab7713b05223f029bf9201daf42096d3b Mon Sep 17 00:00:00 2001 From: Thiago Macieira Date: Fri, 27 Jan 2017 13:09:55 -0800 Subject: x86: Add detection of the AES and SHA New Instructions The AES instructions were first introduced with the Westmere shrink (22nm) of the Nehalem architecture. The SHA instructions are still pending on Intel architecture, but is available on AMD family 17h (gcc argument -march=znver1). Both features operate on SSE registers, so that's why the MSVC command- line argument is the SSE2 one and the configure-time tests depend on features.sse2. The qmake feature names end in "ni" because "aes" and "sha" are too simple and could clash with other uses. The QT_COMPILER_SUPPORTS_ macro doesn't have the "NI" suffix because it has to match the GCC/Clang predefined macro. Change-Id: I445bb15619f6401494e8fffd149dbd1f862ff51c Reviewed-by: Allan Sandfeld Jensen --- mkspecs/win32-icc/qmake.conf | 2 ++ 1 file changed, 2 insertions(+) (limited to 'mkspecs/win32-icc/qmake.conf') diff --git a/mkspecs/win32-icc/qmake.conf b/mkspecs/win32-icc/qmake.conf index 6e2589b4c4..9a86407043 100644 --- a/mkspecs/win32-icc/qmake.conf +++ b/mkspecs/win32-icc/qmake.conf @@ -33,6 +33,8 @@ QMAKE_CFLAGS_AVX512PF += -QxMIC-AVX512 QMAKE_CFLAGS_AVX512DQ += -QxCORE-AVX512 QMAKE_CFLAGS_AVX512BW += -QxCORE-AVX512 QMAKE_CFLAGS_AVX512VL += -QxCORE-AVX512 +QMAKE_CFLAGS_AESNI = -QxSSE2 +QMAKE_CFLAGS_SHANI = -QxSSE4.2 QMAKE_CXX = $$QMAKE_CC QMAKE_CXXFLAGS = $$QMAKE_CFLAGS /Zc:forScope -- cgit v1.2.3