From dc5388e79b71d796c1207681235cf007c39810bd Mon Sep 17 00:00:00 2001 From: Thiago Macieira Date: Sun, 31 Jul 2011 18:57:16 -0300 Subject: Port the ARM atomics to the new QBasicAtomicXXX architecture The implementation is divided in two files, as it used to be in the previous implementation: one for ARMv5, one for ARMv6 and up. For the ARMv5 implementation: Drop the non-Linux EABI version of the atomics, as it's not ABI-compatible with the ARMv6 and ARMv7 implementations. This means this ARMv5 implementation only works on Linux. If other systems implement kernel helpers like Linux, they can be added too. We use the __kernel_cmpxchg located at 0xffff0fc0 to implement the operations, except for fetchAndStore, for which we use the SWP instruction. Also introduce the use of __kernel_dmb (at 0xffff0fa0) for the memory barrier. Now this code is SMP-safe even when built with ARMv5. The kernel cmpxchg helper was introduced in Linux 2.6.12, whereas the dmb helper was introduced in 2.6.15. That means 2.6.15 is the minimum version now. For ARMv6 and up: Introduce byte, half-word and doubleword atomics that work on ARMv6K and up. For ARMv6 specifically, the memory barrier instruction (DMB) isn't present, so we need to accomplish the same with the MCR coprocessor instruction. Change-Id: Ife7f9b920bcc7d1eef7611761f6c59ea940ec7df Reviewed-by: Bradley T. Hughes Reviewed-by: Thiago Macieira --- src/corelib/arch/qatomic_armv6.h | 561 +++++++++++++++++++++++++-------------- 1 file changed, 357 insertions(+), 204 deletions(-) (limited to 'src/corelib/arch/qatomic_armv6.h') diff --git a/src/corelib/arch/qatomic_armv6.h b/src/corelib/arch/qatomic_armv6.h index b25c413e43..21ad24d681 100644 --- a/src/corelib/arch/qatomic_armv6.h +++ b/src/corelib/arch/qatomic_armv6.h @@ -1,7 +1,7 @@ /**************************************************************************** ** ** Copyright (C) 2012 Nokia Corporation and/or its subsidiary(-ies). -** All rights reserved. +** Copyright (C) 2011 Thiago Macieira ** Contact: http://www.qt-project.org/ ** ** This file is part of the QtCore module of the Qt Toolkit. @@ -42,77 +42,72 @@ #ifndef QATOMIC_ARMV6_H #define QATOMIC_ARMV6_H +#include + QT_BEGIN_HEADER QT_BEGIN_NAMESPACE -#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE - -inline bool QBasicAtomicInt::isReferenceCountingNative() -{ return true; } -inline bool QBasicAtomicInt::isReferenceCountingWaitFree() -{ return false; } +#if 0 +#pragma qt_sync_stop_processing +#endif +#define Q_ATOMIC_INT_REFERENCE_COUNTING_IS_ALWAYS_NATIVE #define Q_ATOMIC_INT_TEST_AND_SET_IS_ALWAYS_NATIVE - -inline bool QBasicAtomicInt::isTestAndSetNative() -{ return true; } -inline bool QBasicAtomicInt::isTestAndSetWaitFree() -{ return false; } - #define Q_ATOMIC_INT_FETCH_AND_STORE_IS_ALWAYS_NATIVE - -inline bool QBasicAtomicInt::isFetchAndStoreNative() -{ return true; } -inline bool QBasicAtomicInt::isFetchAndStoreWaitFree() -{ return false; } - #define Q_ATOMIC_INT_FETCH_AND_ADD_IS_ALWAYS_NATIVE -inline bool QBasicAtomicInt::isFetchAndAddNative() -{ return true; } -inline bool QBasicAtomicInt::isFetchAndAddWaitFree() -{ return false; } +#define Q_ATOMIC_INT32_IS_SUPPORTED +#define Q_ATOMIC_INT32_REFERENCE_COUNTING_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT32_TEST_AND_SET_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT32_FETCH_AND_STORE_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT32_FETCH_AND_ADD_IS_ALWAYS_NATIVE #define Q_ATOMIC_POINTER_TEST_AND_SET_IS_ALWAYS_NATIVE +#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE +#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isTestAndSetNative() -{ return true; } -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isTestAndSetWaitFree() -{ return false; } +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; -#define Q_ATOMIC_POINTER_FETCH_AND_STORE_IS_ALWAYS_NATIVE +template struct QBasicAtomicOps: QGenericAtomicOps > +{ + static void orderedMemoryFence(); -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isFetchAndStoreNative() -{ return true; } -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isFetchAndStoreWaitFree() -{ return false; } + static inline bool isReferenceCountingNative() { return true; } + template static bool ref(T &_q_value); + template static bool deref(T &_q_value); -#define Q_ATOMIC_POINTER_FETCH_AND_ADD_IS_ALWAYS_NATIVE + static inline bool isTestAndSetNative() { return true; } + static inline bool isTestAndSetWaitFree() { return false; } + template static bool testAndSetRelaxed(T &_q_value, T expectedValue, T newValue); -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isFetchAndAddNative() -{ return true; } -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::isFetchAndAddWaitFree() -{ return false; } + static inline bool isFetchAndStoreNative() { return true; } + template static T fetchAndStoreRelaxed(T &_q_value, T newValue); + + static inline bool isFetchAndAddNative() { return true; } + template static + T fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType::AdditiveT valueToAdd); +}; + +template struct QAtomicOps : QBasicAtomicOps +{ + typedef T Type; +}; #ifndef Q_CC_RVCT #ifndef Q_DATA_MEMORY_BARRIER -# define Q_DATA_MEMORY_BARRIER asm volatile("":::"memory") +# define Q_DATA_MEMORY_BARRIER asm volatile("mcr p15, 0, r0, c7, c10, 5":::"memory") #endif #ifndef Q_COMPILER_MEMORY_BARRIER # define Q_COMPILER_MEMORY_BARRIER asm volatile("":::"memory") #endif -inline bool QBasicAtomicInt::ref() +template<> template inline +bool QBasicAtomicOps<4>::ref(T &_q_value) { - register int newValue; + register T newValue; register int result; asm volatile("0:\n" "ldrex %[newValue], [%[_q_value]]\n" @@ -128,9 +123,10 @@ inline bool QBasicAtomicInt::ref() return newValue != 0; } -inline bool QBasicAtomicInt::deref() +template<> template inline +bool QBasicAtomicOps<4>::deref(T &_q_value) { - register int newValue; + register T newValue; register int result; asm volatile("0:\n" "ldrex %[newValue], [%[_q_value]]\n" @@ -146,7 +142,8 @@ inline bool QBasicAtomicInt::deref() return newValue != 0; } -inline bool QBasicAtomicInt::testAndSetRelaxed(int expectedValue, int newValue) +template<> template inline +bool QBasicAtomicOps<4>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue) { register int result; asm volatile("0:\n" @@ -165,9 +162,10 @@ inline bool QBasicAtomicInt::testAndSetRelaxed(int expectedValue, int newValue) return result == 0; } -inline int QBasicAtomicInt::fetchAndStoreRelaxed(int newValue) +template<> template inline +T QBasicAtomicOps<4>::fetchAndStoreRelaxed(T &_q_value, T newValue) { - register int originalValue; + register T originalValue; register int result; asm volatile("0:\n" "ldrex %[originalValue], [%[_q_value]]\n" @@ -183,10 +181,11 @@ inline int QBasicAtomicInt::fetchAndStoreRelaxed(int newValue) return originalValue; } -inline int QBasicAtomicInt::fetchAndAddRelaxed(int valueToAdd) +template<> template inline +T QBasicAtomicOps<4>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType::AdditiveT valueToAdd) { - register int originalValue; - register int newValue; + register T originalValue; + register T newValue; register int result; asm volatile("0:\n" "ldrex %[originalValue], [%[_q_value]]\n" @@ -198,21 +197,94 @@ inline int QBasicAtomicInt::fetchAndAddRelaxed(int valueToAdd) [newValue] "=&r" (newValue), [result] "=&r" (result), "+m" (_q_value) - : [valueToAdd] "r" (valueToAdd), + : [valueToAdd] "r" (valueToAdd * QAtomicAdditiveType::AddScale), [_q_value] "r" (&_q_value) : "cc"); return originalValue; } -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::testAndSetRelaxed(T *expectedValue, T *newValue) +#if defined(__ARM_ARCH_7__) \ + || defined(__ARM_ARCH_7A__) \ + || defined(__ARM_ARCH_7R__) \ + || defined(__ARM_ARCH_7M__) \ + || defined(__ARM_ARCH_6K__) +// LDREXB, LDREXH and LDREXD are available on ARMv6K or higher + +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; +template<> struct QAtomicIntegerTraits { enum { IsInteger = 1 }; }; + +#define Q_ATOMIC_INT8_IS_SUPPORTED +#define Q_ATOMIC_INT8_REFERENCE_COUNTING_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT8_TEST_AND_SET_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT8_FETCH_AND_STORE_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT8_FETCH_AND_ADD_IS_ALWAYS_NATIVE + +#define Q_ATOMIC_INT16_IS_SUPPORTED +#define Q_ATOMIC_INT16_REFERENCE_COUNTING_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT16_TEST_AND_SET_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT16_FETCH_AND_STORE_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_ALWAYS_NATIVE + +#define Q_ATOMIC_INT64_IS_SUPPORTED +#define Q_ATOMIC_INT64_REFERENCE_COUNTING_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT64_TEST_AND_SET_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT64_FETCH_AND_STORE_IS_ALWAYS_NATIVE +#define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_ALWAYS_NATIVE + +template<> template inline +bool QBasicAtomicOps<1>::ref(T &_q_value) +{ + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexb %[newValue], [%[_q_value]]\n" + "add %[newValue], %[newValue], #1\n" + "strexb %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<1>::deref(T &_q_value) { - register T *result; + register T newValue; + register int result; asm volatile("0:\n" - "ldrex %[result], [%[_q_value]]\n" + "ldrexb %[newValue], [%[_q_value]]\n" + "sub %[newValue], %[newValue], #1\n" + "strexb %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<1>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue) +{ + register T result; + asm volatile("0:\n" + "ldrexb %[result], [%[_q_value]]\n" "eors %[result], %[result], %[expectedValue]\n" "itt eq\n" - "strexeq %[result], %[newValue], [%[_q_value]]\n" + "strexbeq %[result], %[newValue], [%[_q_value]]\n" "teqeq %[result], #1\n" "beq 0b\n" : [result] "=&r" (result), @@ -224,14 +296,14 @@ Q_INLINE_TEMPLATE bool QBasicAtomicPointer::testAndSetRelaxed(T *expectedValu return result == 0; } -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndStoreRelaxed(T *newValue) +template<> template inline +T QBasicAtomicOps<1>::fetchAndStoreRelaxed(T &_q_value, T newValue) { - register T *originalValue; + register T originalValue; register int result; asm volatile("0:\n" - "ldrex %[originalValue], [%[_q_value]]\n" - "strex %[result], %[newValue], [%[_q_value]]\n" + "ldrexb %[originalValue], [%[_q_value]]\n" + "strexb %[result], %[newValue], [%[_q_value]]\n" "teq %[result], #0\n" "bne 0b\n" : [originalValue] "=&r" (originalValue), @@ -243,28 +315,239 @@ Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndStoreRelaxed(T *newValue) return originalValue; } -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndAddRelaxed(qptrdiff valueToAdd) +template<> template inline +T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType::AdditiveT valueToAdd) { - register T *originalValue; - register T *newValue; + register T originalValue; + register T newValue; register int result; asm volatile("0:\n" - "ldrex %[originalValue], [%[_q_value]]\n" + "ldrexb %[originalValue], [%[_q_value]]\n" "add %[newValue], %[originalValue], %[valueToAdd]\n" - "strex %[result], %[newValue], [%[_q_value]]\n" + "strexb %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [originalValue] "=&r" (originalValue), + [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [valueToAdd] "r" (valueToAdd * QAtomicAdditiveType::AddScale), + [_q_value] "r" (&_q_value) + : "cc"); + return originalValue; +} + +template<> template inline +bool QBasicAtomicOps<2>::ref(T &_q_value) +{ + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexh %[newValue], [%[_q_value]]\n" + "add %[newValue], %[newValue], #1\n" + "strexh %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<2>::deref(T &_q_value) +{ + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexh %[newValue], [%[_q_value]]\n" + "sub %[newValue], %[newValue], #1\n" + "strexh %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<2>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue) +{ + register T result; + asm volatile("0:\n" + "ldrexh %[result], [%[_q_value]]\n" + "eors %[result], %[result], %[expectedValue]\n" + "strexheq %[result], %[newValue], [%[_q_value]]\n" + "teqeq %[result], #1\n" + "beq 0b\n" + : [result] "=&r" (result), + "+m" (_q_value) + : [expectedValue] "r" (expectedValue), + [newValue] "r" (newValue), + [_q_value] "r" (&_q_value) + : "cc"); + return result == 0; +} + +template<> template inline +T QBasicAtomicOps<2>::fetchAndStoreRelaxed(T &_q_value, T newValue) +{ + register T originalValue; + register int result; + asm volatile("0:\n" + "ldrexh %[originalValue], [%[_q_value]]\n" + "strexh %[result], %[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [originalValue] "=&r" (originalValue), + [result] "=&r" (result), + "+m" (_q_value) + : [newValue] "r" (newValue), + [_q_value] "r" (&_q_value) + : "cc"); + return originalValue; +} + +template<> template inline +T QBasicAtomicOps<2>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType::AdditiveT valueToAdd) +{ + register T originalValue; + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexh %[originalValue], [%[_q_value]]\n" + "add %[newValue], %[originalValue], %[valueToAdd]\n" + "strexh %[result], %[newValue], [%[_q_value]]\n" "teq %[result], #0\n" "bne 0b\n" : [originalValue] "=&r" (originalValue), [newValue] "=&r" (newValue), [result] "=&r" (result), "+m" (_q_value) - : [valueToAdd] "r" (valueToAdd * sizeof(T)), + : [valueToAdd] "r" (valueToAdd * QAtomicAdditiveType::AddScale), [_q_value] "r" (&_q_value) : "cc"); return originalValue; } +// Explanation from GCC's source code (config/arm/arm.c) on the modifiers below: +// Whenever you use "r" (dwordVariable), you get assigned a register pair: +// %[reg] - lower-numbered register +// %H[reg] - higher-numbered register +// %Q[reg] - low part of the value +// %R[reg] - high part of the value +// If this is a little-endian build, H and R are the same; otherwise, H and Q are the same. + +template<> template inline +bool QBasicAtomicOps<8>::ref(T &_q_value) +{ + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexd %[newValue], %H[newValue], [%[_q_value]]\n" + "adds %Q[newValue], %Q[newValue], #1\n" + "adc %R[newValue], %R[newValue], #0\n" + "strexd %[result], %[newValue], %H[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<8>::deref(T &_q_value) +{ + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexd %[newValue], %H[newValue], [%[_q_value]]\n" + "subs %Q[newValue], %Q[newValue], #1\n" + "sbc %R[newValue], %R[newValue], #0\n" + "strexd %[result], %[newValue], %H[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [_q_value] "r" (&_q_value) + : "cc", "memory"); + return newValue != 0; +} + +template<> template inline +bool QBasicAtomicOps<8>::testAndSetRelaxed(T &_q_value, T expectedValue, T newValue) +{ + register T result; + asm volatile("0:\n" + "ldrexd %[result], %H[result], [%[_q_value]]\n" + "eor %[result], %[result], %[expectedValue]\n" + "eor %H[result], %H[result], %H[expectedValue]\n" + "orrs %[result], %[result], %H[result]\n" + "strexdeq %[result], %[newValue], %H[newValue], [%[_q_value]]\n" + "teqeq %[result], #1\n" + "beq 0b\n" + : [result] "=&r" (result), + "+m" (_q_value) + : [expectedValue] "r" (expectedValue), + [newValue] "r" (newValue), + [_q_value] "r" (&_q_value) + : "cc"); + return quint32(result) == 0; +} + +template<> template inline +T QBasicAtomicOps<8>::fetchAndStoreRelaxed(T &_q_value, T newValue) +{ + register T originalValue; + register int result; + asm volatile("0:\n" + "ldrexd %[originalValue], %H[originalValue], [%[_q_value]]\n" + "strexd %[result], %[newValue], %H[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [originalValue] "=&r" (originalValue), + [result] "=&r" (result), + "+m" (_q_value) + : [newValue] "r" (newValue), + [_q_value] "r" (&_q_value) + : "cc"); + return originalValue; +} + +template<> template inline +T QBasicAtomicOps<8>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveType::AdditiveT valueToAdd) +{ + register T originalValue; + register T newValue; + register int result; + asm volatile("0:\n" + "ldrexd %[originalValue], %H[originalValue], [%[_q_value]]\n" + "adds %Q[newValue], %Q[originalValue], %Q[valueToAdd]\n" + "adc %R[newValue], %R[originalValue], %R[valueToAdd]\n" + "strexd %[result], %[newValue], %H[newValue], [%[_q_value]]\n" + "teq %[result], #0\n" + "bne 0b\n" + : [originalValue] "=&r" (originalValue), + [newValue] "=&r" (newValue), + [result] "=&r" (result), + "+m" (_q_value) + : [valueToAdd] "r" (valueToAdd * QAtomicAdditiveType::AddScale), + [_q_value] "r" (&_q_value) + : "cc"); + return originalValue; +} + +#endif + #else // This is Q_CC_RVCT @@ -415,140 +698,10 @@ Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndAddRelaxed(qptrdiff valueTo // common code -inline bool QBasicAtomicInt::testAndSetAcquire(int expectedValue, int newValue) -{ - bool returnValue = testAndSetRelaxed(expectedValue, newValue); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -inline bool QBasicAtomicInt::testAndSetRelease(int expectedValue, int newValue) -{ - Q_DATA_MEMORY_BARRIER; - return testAndSetRelaxed(expectedValue, newValue); -} - -inline bool QBasicAtomicInt::testAndSetOrdered(int expectedValue, int newValue) -{ - Q_DATA_MEMORY_BARRIER; - bool returnValue = testAndSetRelaxed(expectedValue, newValue); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; -} - -inline int QBasicAtomicInt::fetchAndStoreAcquire(int newValue) -{ - int returnValue = fetchAndStoreRelaxed(newValue); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -inline int QBasicAtomicInt::fetchAndStoreRelease(int newValue) -{ - Q_DATA_MEMORY_BARRIER; - return fetchAndStoreRelaxed(newValue); -} - -inline int QBasicAtomicInt::fetchAndStoreOrdered(int newValue) -{ - Q_DATA_MEMORY_BARRIER; - int returnValue = fetchAndStoreRelaxed(newValue); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; -} - - -inline int QBasicAtomicInt::fetchAndAddAcquire(int valueToAdd) -{ - int returnValue = fetchAndAddRelaxed(valueToAdd); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -inline int QBasicAtomicInt::fetchAndAddRelease(int valueToAdd) -{ - Q_DATA_MEMORY_BARRIER; - return fetchAndAddRelaxed(valueToAdd); -} - -inline int QBasicAtomicInt::fetchAndAddOrdered(int valueToAdd) -{ - Q_DATA_MEMORY_BARRIER; - int returnValue = fetchAndAddRelaxed(valueToAdd); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::testAndSetAcquire(T *expectedValue, T *newValue) -{ - bool returnValue = testAndSetRelaxed(expectedValue, newValue); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::testAndSetRelease(T *expectedValue, T *newValue) -{ - Q_DATA_MEMORY_BARRIER; - return testAndSetRelaxed(expectedValue, newValue); -} - -template -Q_INLINE_TEMPLATE bool QBasicAtomicPointer::testAndSetOrdered(T *expectedValue, T *newValue) -{ - Q_DATA_MEMORY_BARRIER; - bool returnValue = testAndSetAcquire(expectedValue, newValue); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndStoreAcquire(T *newValue) -{ - T *returnValue = fetchAndStoreRelaxed(newValue); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndStoreRelease(T *newValue) -{ - Q_DATA_MEMORY_BARRIER; - return fetchAndStoreRelaxed(newValue); -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndStoreOrdered(T *newValue) -{ - Q_DATA_MEMORY_BARRIER; - T *returnValue = fetchAndStoreRelaxed(newValue); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndAddAcquire(qptrdiff valueToAdd) -{ - T *returnValue = fetchAndAddRelaxed(valueToAdd); - Q_DATA_MEMORY_BARRIER; - return returnValue; -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndAddRelease(qptrdiff valueToAdd) -{ - Q_DATA_MEMORY_BARRIER; - return fetchAndAddRelaxed(valueToAdd); -} - -template -Q_INLINE_TEMPLATE T *QBasicAtomicPointer::fetchAndAddOrdered(qptrdiff valueToAdd) +template inline +void QBasicAtomicOps::orderedMemoryFence() { Q_DATA_MEMORY_BARRIER; - T *returnValue = fetchAndAddRelaxed(valueToAdd); - Q_COMPILER_MEMORY_BARRIER; - return returnValue; } #undef Q_DATA_MEMORY_BARRIER -- cgit v1.2.3