From fca917c1cc7c941ab6de88757e3c65cf0ca0aabe Mon Sep 17 00:00:00 2001 From: Thiago Macieira Date: Fri, 6 Dec 2013 18:09:05 -0800 Subject: Disable 64-bit atomics on 32-bit x86 MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit At least with GCC, the use of cmpxchg8b in inline assembly is unreliable. The instruction requires 5 registers to be used and sometimes GCC complains that it runs out of them. qatomic_x86.h:424:33: error: can’t find a register in class ‘GENERAL_REGS’ while reloading ‘asm’ qatomic_x86.h:424:33: error: ‘asm’ operand has impossible constraints Change-Id: Ie5414f3bccc6e559c7eec93beabe8663ab40271f Reviewed-by: Olivier Goffart --- src/corelib/arch/qatomic_x86.h | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/corelib/arch') diff --git a/src/corelib/arch/qatomic_x86.h b/src/corelib/arch/qatomic_x86.h index f8180ad9d6..608b3db0ff 100644 --- a/src/corelib/arch/qatomic_x86.h +++ b/src/corelib/arch/qatomic_x86.h @@ -339,6 +339,8 @@ T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveTy #define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_ALWAYS_NATIVE #define Q_ATOMIC_INT16_FETCH_AND_ADD_IS_WAIT_FREE +#ifdef Q_PROCESSOR_X86_64 + #define Q_ATOMIC_INT64_IS_SUPPORTED #define Q_ATOMIC_INT64_REFERENCE_COUNTING_IS_ALWAYS_NATIVE @@ -353,7 +355,6 @@ T QBasicAtomicOps<1>::fetchAndAddRelaxed(T &_q_value, typename QAtomicAdditiveTy #define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_ALWAYS_NATIVE #define Q_ATOMIC_INT64_FETCH_AND_ADD_IS_WAIT_FREE -#ifdef Q_PROCESSOR_X86_64 // native support for 64-bit types template<> template inline bool QBasicAtomicOps<8>::ref(T &_q_value) Q_DECL_NOTHROW -- cgit v1.2.3