From dd91f8d46dbdf62cc276bc204425c4ae106d913e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Lisandro=20Dami=C3=A1n=20Nicanor=20P=C3=A9rez=20Meyer?=
 <perezmeyer@gmail.com>
Date: Fri, 14 Mar 2014 19:33:54 -0300
Subject: Enable sparc detection.

It has been working in Debian for some time.
It also adds detection for 64bits Sparc.

Change-Id: Ie4fc0f58b37672b79191ebe51de0caf2eaf8a1d9
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
---
 src/corelib/global/qprocessordetection.h | 15 +++++++++------
 1 file changed, 9 insertions(+), 6 deletions(-)

(limited to 'src/corelib')

diff --git a/src/corelib/global/qprocessordetection.h b/src/corelib/global/qprocessordetection.h
index 384df8fd54..c9fb728593 100644
--- a/src/corelib/global/qprocessordetection.h
+++ b/src/corelib/global/qprocessordetection.h
@@ -294,12 +294,15 @@
     SPARC is big-endian only prior to V9, while V9 is bi-endian with big-endian
     as the default byte order. Assume all SPARC systems are big-endian.
 */
-// #elif defined(__sparc__)
-// #  define Q_PROCESSOR_SPARC
-// #  if defined(__sparc_v9__)
-// #    define Q_PROCESSOR_SPARC_V9
-// #  endif
-// #  define Q_BYTE_ORDER Q_BIG_ENDIAN
+#elif defined(__sparc__)
+#  define Q_PROCESSOR_SPARC
+#  if defined(__sparc_v9__)
+#    define Q_PROCESSOR_SPARC_V9
+#  endif
+#  if defined(__sparc64__)
+#    define Q_PROCESSOR_SPARC_64
+#  endif
+#  define Q_BYTE_ORDER Q_BIG_ENDIAN
 
 #endif
 
-- 
cgit v1.2.3


From 60b6b28c213a420ee40e254ff1823876098e0a04 Mon Sep 17 00:00:00 2001
From: Aurelien Jarno <aurelien@aurel32.net>
Date: Sun, 10 Nov 2013 23:20:46 +0100
Subject: Support MIPS atomic on pre-MIPS32 architectures
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

The atomic functions on MIPS are based on the sync opcode with an
immediate argument, which is something introduced in the MIPS32
instruction set. This prevent to use Qt on pre-MIPS32 CPU, like the
Loongson 2 CPU.

However some of the pre-MIPS32 CPUs interprets the sync opcode with and
immediate argument as a sync opcode without argument (which is a stronger
ordering than with the argument), and for the others the kernel emulates
it.

It is therefore fine to use the current MIPS atomic functions on
pre-MIPS32 CPU. This patch allows that by temporarily changing the
instruction set to MIPS32 around the sync instruction, so that binutils
doesn't choke on it.

Change-Id: I9cc984bd55b5f172736ce9e638a6f4e271b79fe7
Reviewed-by: Lisandro Damián Nicanor Pérez Meyer <perezmeyer@gmail.com>
Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
---
 src/corelib/arch/qatomic_mips.h | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

(limited to 'src/corelib')

diff --git a/src/corelib/arch/qatomic_mips.h b/src/corelib/arch/qatomic_mips.h
index 463612212b..7bfe16a450 100644
--- a/src/corelib/arch/qatomic_mips.h
+++ b/src/corelib/arch/qatomic_mips.h
@@ -110,13 +110,19 @@ template <typename T> struct QAtomicOps : QBasicAtomicOps<sizeof(T)>
 template <int size> template <typename T> inline
 void QBasicAtomicOps<size>::acquireMemoryFence(const T &) Q_DECL_NOTHROW
 {
-    asm volatile ("sync 0x11" ::: "memory");
+    asm volatile (".set push\n"
+                  ".set mips32\n"
+                  "sync 0x11\n"
+                  ".set pop\n" ::: "memory");
 }
 
 template <int size> template <typename T> inline
 void QBasicAtomicOps<size>::releaseMemoryFence(const T &) Q_DECL_NOTHROW
 {
-    asm volatile ("sync 0x12" ::: "memory");
+    asm volatile (".set push\n"
+                  ".set mips32\n"
+                  "sync 0x11\n"
+                  ".set pop\n" ::: "memory");
 }
 
 template <int size> template <typename T> inline
-- 
cgit v1.2.3