diff options
author | Lars Knoll <lars.knoll@digia.com> | 2014-02-14 12:28:06 +0100 |
---|---|---|
committer | The Qt Project <gerrit-noreply@qt-project.org> | 2014-02-23 15:29:32 +0100 |
commit | 5130f4a679ae38a1d931384188c021112a44065e (patch) | |
tree | d15025f9f7c1a9c6c578ca1b99c0fa5aa9c9b206 | |
parent | cad3ba5fd44c09455c2492548865a8743386ea18 (diff) |
Smaller cleanup
Cleanup the code to generate a swapValues instruction
to only require one code path for 32/64 bit. In
addition, this seems to be slightly faster even on
x86-64.
Change-Id: I0584c3eb5249606ca7541abfbce227e5cb44711f
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
-rw-r--r-- | src/qml/jit/qv4assembler_p.h | 2 | ||||
-rw-r--r-- | src/qml/jit/qv4isel_masm.cpp | 20 |
2 files changed, 7 insertions, 15 deletions
diff --git a/src/qml/jit/qv4assembler_p.h b/src/qml/jit/qv4assembler_p.h index dd1209a026..bc379386d4 100644 --- a/src/qml/jit/qv4assembler_p.h +++ b/src/qml/jit/qv4assembler_p.h @@ -145,6 +145,7 @@ public: static const RegisterID ReturnValueRegister = JSC::X86Registers::eax; static const RegisterID ScratchRegister = JSC::X86Registers::ecx; static const FPRegisterID FPGpr0 = JSC::X86Registers::xmm0; + static const FPRegisterID FPGpr1 = JSC::X86Registers::xmm1; static const int RegisterSize = 4; @@ -227,6 +228,7 @@ public: static const RegisterID ReturnValueRegister = JSC::ARMRegisters::r0; static const RegisterID ScratchRegister = JSC::ARMRegisters::r6; static const FPRegisterID FPGpr0 = JSC::ARMRegisters::d0; + static const FPRegisterID FPGpr1 = JSC::ARMRegisters::d1; static const int RegisterSize = 4; diff --git a/src/qml/jit/qv4isel_masm.cpp b/src/qml/jit/qv4isel_masm.cpp index 035d0fec76..706130e995 100644 --- a/src/qml/jit/qv4isel_masm.cpp +++ b/src/qml/jit/qv4isel_masm.cpp @@ -818,23 +818,13 @@ void InstructionSelection::swapValues(IR::Temp *sourceTemp, IR::Temp *targetTemp } else if (sourceTemp->kind == IR::Temp::StackSlot) { if (targetTemp->kind == IR::Temp::StackSlot) { // Note: a swap for two stack-slots can involve different types. -#if CPU(X86_64) - _as->load64(_as->stackSlotPointer(targetTemp), Assembler::ReturnValueRegister); - _as->load64(_as->stackSlotPointer(sourceTemp), Assembler::ScratchRegister); - _as->store64(Assembler::ScratchRegister, _as->stackSlotPointer(targetTemp)); - _as->store64(Assembler::ReturnValueRegister, _as->stackSlotPointer(sourceTemp)); -#else - Assembler::FPRegisterID tReg = _as->toDoubleRegister(targetTemp); Assembler::Pointer sAddr = _as->stackSlotPointer(sourceTemp); Assembler::Pointer tAddr = _as->stackSlotPointer(targetTemp); - _as->load32(sAddr, Assembler::ScratchRegister); - _as->store32(Assembler::ScratchRegister, tAddr); - sAddr.offset += 4; - tAddr.offset += 4; - _as->load32(sAddr, Assembler::ScratchRegister); - _as->store32(Assembler::ScratchRegister, tAddr); - _as->storeDouble(tReg, _as->stackSlotPointer(sourceTemp)); -#endif + // use the implementation in JSC::MacroAssembler, as it doesn't do bit swizzling + _as->JSC::MacroAssembler::loadDouble(sAddr, Assembler::FPGpr0); + _as->JSC::MacroAssembler::loadDouble(tAddr, Assembler::FPGpr1); + _as->JSC::MacroAssembler::storeDouble(Assembler::FPGpr1, sAddr); + _as->JSC::MacroAssembler::storeDouble(Assembler::FPGpr0, tAddr); return; } } |