diff options
author | Lars Knoll <lars.knoll@qt.io> | 2018-08-06 14:55:21 +0200 |
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committer | Lars Knoll <lars.knoll@qt.io> | 2018-08-10 14:16:09 +0000 |
commit | 18d2f78437d28987297148b63b99ceed6313a78a (patch) | |
tree | 845e016b002a123e394df43fcf88cf2dc7ee1fb6 /src/3rdparty/masm/assembler/ARM64Assembler.h | |
parent | 577630fe4a1f6a129239788080ff9e802118fd26 (diff) |
Update Yarr to the latest version from WebKit
Updated Yarr to a to commit
4d2a53d60487cb1f8b2a9a1e9f684af336fd7d2c in WebKit.
Adjusted the yarr code base to work with our older version of
wtf and masm.
Change-Id: I04b4593ece051e1d7aa087b87aa08c92595d1098
Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
Diffstat (limited to 'src/3rdparty/masm/assembler/ARM64Assembler.h')
-rw-r--r-- | src/3rdparty/masm/assembler/ARM64Assembler.h | 24 |
1 files changed, 24 insertions, 0 deletions
diff --git a/src/3rdparty/masm/assembler/ARM64Assembler.h b/src/3rdparty/masm/assembler/ARM64Assembler.h index 1787e921e8..fcf2e485e8 100644 --- a/src/3rdparty/masm/assembler/ARM64Assembler.h +++ b/src/3rdparty/masm/assembler/ARM64Assembler.h @@ -1980,6 +1980,13 @@ public: } template<int datasize> + ALWAYS_INLINE void stp(RegisterID rt, RegisterID rt2, RegisterID rn, unsigned pimm = 0) + { + CHECK_DATASIZE(); + insn(loadStoreRegisterPairOffset(MEMPAIROPSIZE_INT(datasize), false, MemOp_STORE, pimm, rn, rt, rt2)); + } + + template<int datasize> ALWAYS_INLINE void str(RegisterID rt, RegisterID rn, RegisterID rm) { str<datasize>(rt, rn, rm, UXTX, 0); @@ -3701,6 +3708,23 @@ private: } // 'V' means vector + ALWAYS_INLINE static int loadStoreRegisterPairOffset(MemPairOpSize size, bool V, MemOp opc, int immediate, RegisterID rn, FPRegisterID rt, FPRegisterID rt2) + { + ASSERT(size < 3); + ASSERT(opc == (opc & 1)); // Only load or store, load signed 64 is handled via size. + ASSERT(V || (size != MemPairOp_LoadSigned_32) || (opc == MemOp_LOAD)); // There isn't an integer store signed. + unsigned immedShiftAmount = memPairOffsetShift(V, size); + int imm7 = immediate >> immedShiftAmount; + ASSERT((imm7 << immedShiftAmount) == immediate && isInt7(imm7)); + return (0x29000000 | size << 30 | V << 26 | opc << 22 | (imm7 & 0x7f) << 15 | rt2 << 10 | xOrSp(rn) << 5 | rt); + } + + ALWAYS_INLINE static int loadStoreRegisterPairOffset(MemPairOpSize size, bool V, MemOp opc, int immediate, RegisterID rn, RegisterID rt, RegisterID rt2) + { + return loadStoreRegisterPairOffset(size, V, opc, immediate, rn, xOrZrAsFPR(rt), xOrZrAsFPR(rt2)); + } + + // 'V' means vector // 'S' means shift rm ALWAYS_INLINE static int loadStoreRegisterRegisterOffset(MemOpSize size, bool V, MemOp opc, RegisterID rm, ExtendType option, bool S, RegisterID rn, FPRegisterID rt) { |