diff options
author | Simon Hausmann <simon.hausmann@digia.com> | 2013-04-12 12:58:29 +0200 |
---|---|---|
committer | Lars Knoll <lars.knoll@digia.com> | 2013-04-12 17:30:06 +0200 |
commit | fd09b7d9b54ccb4d737747ee7fba26f15f4901cd (patch) | |
tree | cb8b68211b0eff5c2b4927182c93749b053edb71 /src/3rdparty/masm/assembler/ARMAssembler.cpp | |
parent | 89be8e111c34bf6e96710e574c251587dd59f42b (diff) |
WTF/JSC update to r148273
This brings in various bug fixes in the ARM and MIPS assemblers as well as
a Yarr crash fix and performance fix.
This change doesn't compile as-is, but the next change will
apply the modifications necessary to compile. That'll make future updates
easier as it allows for cherry-picking because the modifications are usually
always the same.
Change-Id: Iac32f62c71e8ff908deb41f28f12fbc98c0823e1
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Diffstat (limited to 'src/3rdparty/masm/assembler/ARMAssembler.cpp')
-rw-r--r-- | src/3rdparty/masm/assembler/ARMAssembler.cpp | 24 |
1 files changed, 20 insertions, 4 deletions
diff --git a/src/3rdparty/masm/assembler/ARMAssembler.cpp b/src/3rdparty/masm/assembler/ARMAssembler.cpp index 9655557a5d..6912d1ea39 100644 --- a/src/3rdparty/masm/assembler/ARMAssembler.cpp +++ b/src/3rdparty/masm/assembler/ARMAssembler.cpp @@ -297,8 +297,15 @@ void ARMAssembler::baseIndexTransfer32(DataTransferTypeA transferType, RegisterI return; } - add(ARMRegisters::S1, base, op2); - dataTransfer32(transferType, srcDst, ARMRegisters::S1, offset); + if (offset <= 0xfffff && offset >= -0xfffff) { + add(ARMRegisters::S0, base, op2); + dataTransfer32(transferType, srcDst, ARMRegisters::S0, offset); + return; + } + + moveImm(offset, ARMRegisters::S0); + add(ARMRegisters::S0, ARMRegisters::S0, op2); + dtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } void ARMAssembler::dataTransfer16(DataTransferTypeB transferType, RegisterID srcDst, RegisterID base, int32_t offset) @@ -333,8 +340,17 @@ void ARMAssembler::baseIndexTransfer16(DataTransferTypeB transferType, RegisterI return; } - add(ARMRegisters::S1, base, lsl(index, scale)); - dataTransfer16(transferType, srcDst, ARMRegisters::S1, offset); + ARMWord op2 = lsl(index, scale); + + if (offset <= 0xffff && offset >= -0xffff) { + add(ARMRegisters::S0, base, op2); + dataTransfer16(transferType, srcDst, ARMRegisters::S0, offset); + return; + } + + moveImm(offset, ARMRegisters::S0); + add(ARMRegisters::S0, ARMRegisters::S0, op2); + halfDtrUpRegister(transferType, srcDst, base, ARMRegisters::S0); } void ARMAssembler::dataTransferFloat(DataTransferTypeFloat transferType, FPRegisterID srcDst, RegisterID base, int32_t offset) |