diff options
| author | Lars Knoll <lars.knoll@digia.com> | 2013-10-04 15:38:42 +0200 |
|---|---|---|
| committer | The Qt Project <gerrit-noreply@qt-project.org> | 2013-10-11 16:01:24 +0200 |
| commit | f6de6160b915b5a35e75746a35c4ef94ceb9b2c2 (patch) | |
| tree | b75e37bc0579a2195c36074999cd4b116aeb7a1f /src/3rdparty/masm | |
| parent | 886c359ebb86afcad3a62ce6cf7697fd7d6a1ea8 (diff) | |
Optimise code generation for convertTypeToSInt32
Add 64 bit code patch and avoid some duplicated
calculation in 32 bit mode
Change-Id: I0e111de8ac4e733aa8802c49b4b15d785688d7ea
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/3rdparty/masm')
| -rw-r--r-- | src/3rdparty/masm/assembler/MacroAssemblerX86Common.h | 4 | ||||
| -rw-r--r-- | src/3rdparty/masm/assembler/MacroAssemblerX86_64.h | 10 | ||||
| -rw-r--r-- | src/3rdparty/masm/assembler/X86Assembler.h | 23 |
3 files changed, 35 insertions, 2 deletions
diff --git a/src/3rdparty/masm/assembler/MacroAssemblerX86Common.h b/src/3rdparty/masm/assembler/MacroAssemblerX86Common.h index 53cb80c210..520cf915fa 100644 --- a/src/3rdparty/masm/assembler/MacroAssemblerX86Common.h +++ b/src/3rdparty/masm/assembler/MacroAssemblerX86Common.h @@ -318,7 +318,7 @@ public: { m_assembler.sarl_i8r(imm.m_value, dest); } - + void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest) { if (src != dest) @@ -362,7 +362,7 @@ public: move(src, dest); urshift32(imm, dest); } - + void sub32(RegisterID src, RegisterID dest) { m_assembler.subl_rr(src, dest); diff --git a/src/3rdparty/masm/assembler/MacroAssemblerX86_64.h b/src/3rdparty/masm/assembler/MacroAssemblerX86_64.h index 3aaa0fd1bc..db0e880cb9 100644 --- a/src/3rdparty/masm/assembler/MacroAssemblerX86_64.h +++ b/src/3rdparty/masm/assembler/MacroAssemblerX86_64.h @@ -295,6 +295,16 @@ public: m_assembler.xorq_ir(imm.m_value, srcDest); } + void urshift64(TrustedImm32 imm, RegisterID dest) + { + m_assembler.shrq_i8r(imm.m_value, dest); + } + + void lshift64(TrustedImm32 imm, RegisterID dest) + { + m_assembler.shlq_i8r(imm.m_value, dest); + } + void load64(ImplicitAddress address, RegisterID dest) { m_assembler.movq_mr(address.offset, address.base, dest); diff --git a/src/3rdparty/masm/assembler/X86Assembler.h b/src/3rdparty/masm/assembler/X86Assembler.h index a3a480541c..1875ebaff0 100644 --- a/src/3rdparty/masm/assembler/X86Assembler.h +++ b/src/3rdparty/masm/assembler/X86Assembler.h @@ -683,6 +683,29 @@ public: } } + void shrq_i8r(int imm, RegisterID dst) + { + // ### doesn't work when removing the "0 &&" + if (0 && imm == 1) + m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHR, dst); + else { + m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SHR, dst); + m_formatter.immediate8(imm); + } + } + + void shlq_i8r(int imm, RegisterID dst) + { + // ### doesn't work when removing the "0 &&" + if (0 && imm == 1) + m_formatter.oneByteOp64(OP_GROUP2_Ev1, GROUP2_OP_SHL, dst); + else { + m_formatter.oneByteOp64(OP_GROUP2_EvIb, GROUP2_OP_SHL, dst); + m_formatter.immediate8(imm); + } + } + + #endif void sarl_i8r(int imm, RegisterID dst) |