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| author | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-04-11 10:30:45 +0200 |
|---|---|---|
| committer | The Qt Project <gerrit-noreply@qt-project.org> | 2014-04-15 15:27:12 +0200 |
| commit | 63f757faea7008e478e0a1edea4f0ae79aaba5f7 (patch) | |
| tree | 52e63f585b68771a7dad4440de162f58a05bd6dc /src/3rdparty | |
| parent | 926a98eb5e3f1eb7f872f7c94812589abd18a90d (diff) | |
V4 JIT: fix constant shifts.
Do not generate constant shifts of 0. We do not use the flags, so it's a
move. On ARM it's actually important not to do this, because lsr/asr
with imm=0 is a special case (shift of 32 bits).
When in the area, also skip generating an and of the second operand with
0x1f. For Intel this is done on the CPU, and for ARM the JSC assembler
will generate it for us.
This patch also updates the ARM disassembler to print the right
immediate values for the shifts.
Change-Id: I7c92c8d899352712c84e5534c48392d75466be0e
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/3rdparty')
| -rw-r--r-- | src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp | 4 | ||||
| -rw-r--r-- | src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h | 6 |
2 files changed, 7 insertions, 3 deletions
diff --git a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp index 81063e2b11..ae7b0859ed 100644 --- a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp +++ b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp @@ -49,7 +49,7 @@ const char* const ARMv7DOpcode::s_optionName[8] = { }; const char* const ARMv7DOpcode::s_shiftNames[4] = { - "lsl", "lsr", "asl", "ror" + "lsl", "lsr", "asr", "ror" }; const char* const ARMv7DOpcode::s_specialRegisterNames[3] = { "sp", "lr", "pc" }; @@ -944,7 +944,7 @@ const char* ARMv7DOpcodeDataProcessingShiftedReg::format() appendSeparator(); appendRegisterName(rm()); appendSeparator(); - appendUnsignedImmediate(immediate5()); + appendImmShift(type(), immediate5()); return m_formatBuffer; } diff --git a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h index ca5f955ba1..5bcb6b15b9 100644 --- a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h +++ b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h @@ -69,6 +69,7 @@ protected: static const char* conditionName(unsigned condition) { return s_conditionNames[condition & 0xf]; } static const char* shiftName(unsigned shiftValue) { return s_shiftNames[shiftValue & 0x3]; } + static bool isRightShift(unsigned shiftValue) { return shiftValue == 1 || shiftValue == 2; } bool inITBlock() { return m_ITConditionIndex < m_ITBlocksize; } bool startingITBlock() { return m_ITConditionIndex == m_ITBlocksize + 1; } @@ -514,7 +515,10 @@ protected: const char* opName() { return shiftName(op()); } unsigned op() { return (m_opcode >> 12) & 0x3; } - unsigned immediate5() { return (m_opcode >> 6) & 0x1f; } + unsigned immediate5() { + unsigned imm = (m_opcode >> 6) & 0x1f; + return isRightShift(op()) && imm == 0 ? 32 : imm; + } }; class ARMv7DOpcodeMiscAddSubSP : public ARMv7D16BitOpcode { |