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authorLars Knoll <lars.knoll@digia.com>2013-10-29 15:28:17 +0100
committerThe Qt Project <gerrit-noreply@qt-project.org>2013-10-30 08:29:49 +0100
commit53a6d572e5ded9f559a7287e42a65328b4e8ba1b (patch)
tree8b45ebec1ae68a9fce78e0e907ec02650e7dbce7 /src/qml/compiler/qv4isel_moth.cpp
parent906d5c5c40183468f9521277c6244a6c46730de6 (diff)
Moth: Inline a couple of binops
This gives another 10-15% for v8-bench Change-Id: Iaea90402179813af23008c35d344fa7f5353cf5f Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/qml/compiler/qv4isel_moth.cpp')
-rw-r--r--src/qml/compiler/qv4isel_moth.cpp57
1 files changed, 57 insertions, 0 deletions
diff --git a/src/qml/compiler/qv4isel_moth.cpp b/src/qml/compiler/qv4isel_moth.cpp
index 2db30aa7f8..cddfc0076b 100644
--- a/src/qml/compiler/qv4isel_moth.cpp
+++ b/src/qml/compiler/qv4isel_moth.cpp
@@ -560,6 +560,14 @@ void InstructionSelection::unop(V4IR::AluOp oper, V4IR::Temp *sourceTemp, V4IR::
return;
}
case V4IR::OpUPlus: {
+ if (isNumberType(sourceTemp)) {
+ // use a move
+ Instruction::Move move;
+ move.source = getParam(sourceTemp);
+ move.result = getResultParam(targetTemp);
+ addInstruction(move);
+ return;
+ }
Instruction::UPlus uplus;
uplus.source = getParam(sourceTemp);
uplus.result = getResultParam(targetTemp);
@@ -634,6 +642,55 @@ Param InstructionSelection::binopHelper(V4IR::AluOp oper, V4IR::Expr *leftSource
if (_stackSlotAllocator && target && leftSource->asTemp())
_stackSlotAllocator->addHint(*leftSource->asTemp(), *target);
+ if (oper == V4IR::OpAdd) {
+ Instruction::Add add;
+ add.lhs = getParam(leftSource);
+ add.rhs = getParam(rightSource);
+ add.result = getResultParam(target);
+ addInstruction(add);
+ return add.result;
+ }
+ if (oper == V4IR::OpSub) {
+ Instruction::Sub sub;
+ sub.lhs = getParam(leftSource);
+ sub.rhs = getParam(rightSource);
+ sub.result = getResultParam(target);
+ addInstruction(sub);
+ return sub.result;
+ }
+ if (oper == V4IR::OpMul) {
+ Instruction::Mul mul;
+ mul.lhs = getParam(leftSource);
+ mul.rhs = getParam(rightSource);
+ mul.result = getResultParam(target);
+ addInstruction(mul);
+ return mul.result;
+ }
+ if (oper == V4IR::OpBitAnd) {
+ Instruction::BitAnd bitAnd;
+ bitAnd.lhs = getParam(leftSource);
+ bitAnd.rhs = getParam(rightSource);
+ bitAnd.result = getResultParam(target);
+ addInstruction(bitAnd);
+ return bitAnd.result;
+ }
+ if (oper == V4IR::OpBitOr) {
+ Instruction::BitOr bitOr;
+ bitOr.lhs = getParam(leftSource);
+ bitOr.rhs = getParam(rightSource);
+ bitOr.result = getResultParam(target);
+ addInstruction(bitOr);
+ return bitOr.result;
+ }
+ if (oper == V4IR::OpBitXor) {
+ Instruction::BitXor bitXor;
+ bitXor.lhs = getParam(leftSource);
+ bitXor.rhs = getParam(rightSource);
+ bitXor.result = getResultParam(target);
+ addInstruction(bitXor);
+ return bitXor.result;
+ }
+
if (oper == V4IR::OpInstanceof || oper == V4IR::OpIn || oper == V4IR::OpAdd) {
Instruction::BinopContext binop;
if (oper == V4IR::OpInstanceof)