Fix move ordering while resolving edges in register allocation

When register allocation on an IR in SSA form is done, the last step is
to turn the Phi nodes into moves and swaps and put those instructions in
the predecessors. As the Phi nodes are conceptually "executed in
parallel", this can result in cycles:
  r1 <- r0
  r0 <- r1
These have to be turned into a swap instruction. Also, the moves have to
be ordered in order to make sure that no values are overwritten:
  r1 <- r0
  r2 <- r1
Here the two moves need to be switched. The comments in the code
document the algorithm.

Change-Id: I4151988681f7554b00a3eb70d224e6e2f29ebf04
Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>

1 files changed, 10 insertions, 0 deletions

diff --git a/src/qml/compiler/qv4jsir_p.h b/src/qml/compiler/qv4jsir_p.h
index 73aa6c4975..a614d3fe1c 100644
--- a/src/qml/compiler/qv4jsir_p.h
+++ b/src/qml/compiler/qv4jsir_p.h
@@ -507,6 +507,16 @@ struct Q_AUTOTEST_EXPORT Temp: Expr {
         , memberResolver(0)
     {}
 
+    Temp(Type type, Kind kind, unsigned index)
+        : Expr(TempExpr)
+        , index(index)
+        , isReadOnly(0)
+        , kind(kind)
+        , memberResolver(0)
+    {
+        this->type = type;
+    }
+
     void init(unsigned kind, unsigned index)
     {
         this->index = index;