diff options
| author | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-06-27 14:37:50 +0200 |
|---|---|---|
| committer | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-08-12 09:50:28 +0200 |
| commit | 99d0921e2d2a20b956cab172d472f7c369c05008 (patch) | |
| tree | e39b890261ff91862e5c1a0718c3408c41c927a8 /src/qml/compiler/qv4ssa.cpp | |
| parent | 430853836f9c17154ef3ee4cac6b03b90ee493a9 (diff) | |
V4 JIT: tune generated instructions for inplace binops
Generate better code for in-place binary operations where the right-hand
side is either a constant or a memory address. Now that the JIT can do
this, also tell the register allocator not to un-spill that right-hand
side.
Change-Id: I0ab852f6b92f90dfed99c05fbaf91aad2549ecf4
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/qml/compiler/qv4ssa.cpp')
| -rw-r--r-- | src/qml/compiler/qv4ssa.cpp | 17 |
1 files changed, 13 insertions, 4 deletions
diff --git a/src/qml/compiler/qv4ssa.cpp b/src/qml/compiler/qv4ssa.cpp index 5e9401afc3..8c5f2e30bb 100644 --- a/src/qml/compiler/qv4ssa.cpp +++ b/src/qml/compiler/qv4ssa.cpp @@ -3887,13 +3887,22 @@ void optimizeSSA(StatementWorklist &W, DefUses &defUses, DominatorTree &df) continue; } } - if (rightConst) { // mask right hand side of shift operations + if (rightConst) { switch (binop->op) { case OpLShift: case OpRShift: - case OpURShift: - rightConst->value = QV4::Primitive::toInt32(rightConst->value) & 0x1f; - rightConst->type = SInt32Type; + if (double v = QV4::Primitive::toInt32(rightConst->value) & 0x1f) { + // mask right hand side of shift operations + rightConst->value = v; + rightConst->type = SInt32Type; + } else { + // shifting a value over 0 bits is a move: + if (rightConst->value == 0) { + m->source = binop->left; + W += m; + } + } + break; default: break; |