diff options
| author | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-07-22 11:56:33 +0200 |
|---|---|---|
| committer | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-08-12 12:30:34 +0200 |
| commit | 4ad1b63f257ac033e3876130f39eba3325363de5 (patch) | |
| tree | e617b30d8afa3ae0f132396fb70857e22cc6121f /src/qml/jit/qv4assembler.cpp | |
| parent | f87d2a40ef2f20a11ed1353ed59ef8ced2cecb00 (diff) | |
V4 JIT: generate code for int32 comparisons.
Change-Id: I5e88fb3df7b01f4f515ce4d2e451a5a6f5ba92ad
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/qml/jit/qv4assembler.cpp')
| -rw-r--r-- | src/qml/jit/qv4assembler.cpp | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/src/qml/jit/qv4assembler.cpp b/src/qml/jit/qv4assembler.cpp index 1e9669acd5..3f3fccb39d 100644 --- a/src/qml/jit/qv4assembler.cpp +++ b/src/qml/jit/qv4assembler.cpp @@ -365,5 +365,27 @@ Assembler::Jump Assembler::branchDouble(bool invertCondition, IR::AluOp op, return JSC::MacroAssembler::branchDouble(cond, toDoubleRegister(left, FPGpr0), toDoubleRegister(right, FPGpr1)); } +Assembler::Jump Assembler::branchInt32(bool invertCondition, IR::AluOp op, IR::Expr *left, IR::Expr *right) +{ + Assembler::RelationalCondition cond; + switch (op) { + case IR::OpGt: cond = Assembler::GreaterThan; break; + case IR::OpLt: cond = Assembler::LessThan; break; + case IR::OpGe: cond = Assembler::GreaterThanOrEqual; break; + case IR::OpLe: cond = Assembler::LessThanOrEqual; break; + case IR::OpEqual: + case IR::OpStrictEqual: cond = Assembler::Equal; break; + case IR::OpNotEqual: + case IR::OpStrictNotEqual: cond = Assembler::NotEqual; break; + default: + Q_UNREACHABLE(); + } + if (invertCondition) + cond = JSC::MacroAssembler::invert(cond); + + return JSC::MacroAssembler::branch32(cond, + toInt32Register(left, Assembler::ScratchRegister), + toInt32Register(right, Assembler::ReturnValueRegister)); +} #endif |