diff options
| author | Julien Brianceau <jbriance@cisco.com> | 2015-04-15 09:40:37 +0200 |
|---|---|---|
| committer | Frederik Gladhorn <frederik.gladhorn@theqtcompany.com> | 2015-04-27 15:59:09 +0000 |
| commit | 9d5627ff648cd578c54625dba5158f450779ea8b (patch) | |
| tree | defda99be82e4d9f58ecd5006203ea4743ae6e19 /src/qml/jit/qv4binop.cpp | |
| parent | 5d2f97791ccff58bb945acbc28df65fa0521a1f6 (diff) | |
V4: add JIT support for mips platforms (32-bit) and enable it
[ChangeLog][QtQml] Enabled Just-In-Time compilation for JavaScript on MIPS
Change-Id: Idce070f29645760d6376767ef67e4592828c104d
Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
Diffstat (limited to 'src/qml/jit/qv4binop.cpp')
| -rw-r--r-- | src/qml/jit/qv4binop.cpp | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/qml/jit/qv4binop.cpp b/src/qml/jit/qv4binop.cpp index c6c8023cd7..e4a2846f32 100644 --- a/src/qml/jit/qv4binop.cpp +++ b/src/qml/jit/qv4binop.cpp @@ -415,8 +415,8 @@ bool Binop::int32Binop(IR::Expr *leftSource, IR::Expr *rightSource, IR::Expr *ta case IR::OpAdd: as->add32(l, r, targetReg); break; case IR::OpMul: as->mul32(l, r, targetReg); break; -#if CPU(ARM) || CPU(X86) || CPU(X86_64) - // The ARM assembler will generate an and with 0x1f for us, and Intel will do it on the CPU. +#if CPU(ARM) || CPU(X86) || CPU(X86_64) || CPU(MIPS) + // The ARM assembler will generate an and with 0x1f for us, MIPS and Intel will do it on the CPU. case IR::OpLShift: as->lshift32(l, r, targetReg); break; case IR::OpRShift: as->rshift32(l, r, targetReg); break; |