diff options
| author | Simon Hausmann <simon.hausmann@qt.io> | 2017-01-11 10:39:52 +0100 |
|---|---|---|
| committer | Simon Hausmann <simon.hausmann@qt.io> | 2017-01-28 19:04:46 +0000 |
| commit | b77c9853627357872d2ba2edbb72e98cda87517f (patch) | |
| tree | bf445148f487930101f27c6716621a73bdb703fb /src/qml/jit/qv4binop.cpp | |
| parent | a11278570d6eb3766da6277ccbce0aa96e820d0c (diff) | |
Make QV4::JIT::Assembler a template
We are going to need multiple variants of it in the future.
Change-Id: Ieeec833f911b4cdeb2de4e9afb982b90424cd157
Reviewed-by: Lars Knoll <lars.knoll@qt.io>
Diffstat (limited to 'src/qml/jit/qv4binop.cpp')
| -rw-r--r-- | src/qml/jit/qv4binop.cpp | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/qml/jit/qv4binop.cpp b/src/qml/jit/qv4binop.cpp index df19ddb31c..dfaf7f518c 100644 --- a/src/qml/jit/qv4binop.cpp +++ b/src/qml/jit/qv4binop.cpp @@ -455,18 +455,18 @@ bool Binop<JITAssembler>::int32Binop(IR::Expr *leftSource, IR::Expr *rightSource // Not all CPUs accept shifts over more than 31 bits, and some CPUs (like ARM) will do // surprising stuff when shifting over 0 bits. #define CHECK_RHS(op) { \ - as->and32(TrustedImm32(0x1f), r, Assembler::ScratchRegister); \ - Jump notZero = as->branch32(RelationalCondition::NotEqual, Assembler::ScratchRegister, TrustedImm32(0)); \ + as->and32(TrustedImm32(0x1f), r, JITAssembler::ScratchRegister); \ + Jump notZero = as->branch32(RelationalCondition::NotEqual, JITAssembler::ScratchRegister, TrustedImm32(0)); \ as->move(l, targetReg); \ Jump done = as->jump(); \ notZero.link(as); \ op; \ done.link(as); \ } - case IR::OpLShift: CHECK_RHS(as->lshift32(l, Assembler::ScratchRegister, targetReg)); break; - case IR::OpRShift: CHECK_RHS(as->rshift32(l, Assembler::ScratchRegister, targetReg)); break; + case IR::OpLShift: CHECK_RHS(as->lshift32(l, JITAssembler::ScratchRegister, targetReg)); break; + case IR::OpRShift: CHECK_RHS(as->rshift32(l, JITAssembler::ScratchRegister, targetReg)); break; case IR::OpURShift: - CHECK_RHS(as->urshift32(l, Assembler::ScratchRegister, targetReg)); + CHECK_RHS(as->urshift32(l, JITAssembler::ScratchRegister, targetReg)); as->storeUInt32(targetReg, target); // IMPORTANT: do NOT do a break here! The stored type of an urshift is different from the other binary operations! return true; @@ -576,6 +576,6 @@ typename JITAssembler::Jump Binop<JITAssembler>::genInlineBinop(IR::Expr *leftSo return done; } -template struct QV4::JIT::Binop<QV4::JIT::Assembler>; +template struct QV4::JIT::Binop<QV4::JIT::Assembler<AssemblerTargetConfiguration<DefaultPlatformMacroAssembler>>>; #endif |