Move all binop related code into qv4binop*

Change-Id: I8f96b8d570dd4c0139b0a2e595055b3b2c6dae70
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>

1 files changed, 159 insertions, 0 deletions

diff --git a/src/qml/jit/qv4binop_p.h b/src/qml/jit/qv4binop_p.h
index d29b370f37..096f28e881 100644
--- a/src/qml/jit/qv4binop_p.h
+++ b/src/qml/jit/qv4binop_p.h
@@ -43,6 +43,7 @@
 
 #include <qv4jsir_p.h>
 #include <qv4isel_masm_p.h>
+#include <qv4assembler_p.h>
 
 QT_BEGIN_NAMESPACE
 
@@ -62,6 +63,164 @@ struct Binop {
     bool int32Binop(IR::Expr *leftSource, IR::Expr *rightSource, IR::Temp *target);
     Assembler::Jump genInlineBinop(IR::Expr *leftSource, IR::Expr *rightSource, IR::Temp *target);
 
+    typedef Assembler::Jump (Binop::*MemRegOp)(Assembler::Address, Assembler::RegisterID);
+    typedef Assembler::Jump (Binop::*ImmRegOp)(Assembler::TrustedImm32, Assembler::RegisterID);
+
+    struct OpInfo {
+        const char *name;
+        QV4::BinOp fallbackImplementation;
+        QV4::BinOpContext contextImplementation;
+        MemRegOp inlineMemRegOp;
+        ImmRegOp inlineImmRegOp;
+    };
+
+    static const OpInfo operations[IR::LastAluOp + 1];
+    static const OpInfo &operation(IR::AluOp operation)
+    { return operations[operation]; }
+
+    Assembler::Jump inline_add32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        return as->branchAdd32(Assembler::Overflow, addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        return as->branchAdd32(Assembler::Overflow, Assembler::ScratchRegister, reg);
+#endif
+    }
+
+    Assembler::Jump inline_add32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        return as->branchAdd32(Assembler::Overflow, imm, reg);
+    }
+
+    Assembler::Jump inline_sub32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        return as->branchSub32(Assembler::Overflow, addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        return as->branchSub32(Assembler::Overflow, Assembler::ScratchRegister, reg);
+#endif
+    }
+
+    Assembler::Jump inline_sub32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        return as->branchSub32(Assembler::Overflow, imm, reg);
+    }
+
+    Assembler::Jump inline_mul32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        return as->branchMul32(Assembler::Overflow, addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        return as->branchMul32(Assembler::Overflow, Assembler::ScratchRegister, reg);
+#endif
+    }
+
+    Assembler::Jump inline_mul32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        return as->branchMul32(Assembler::Overflow, imm, reg, reg);
+    }
+
+    Assembler::Jump inline_shl32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+        as->load32(addr, Assembler::ScratchRegister);
+        as->and32(Assembler::TrustedImm32(0x1f), Assembler::ScratchRegister);
+        as->lshift32(Assembler::ScratchRegister, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_shl32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        imm.m_value &= 0x1f;
+        as->lshift32(imm, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_shr32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+        as->load32(addr, Assembler::ScratchRegister);
+        as->and32(Assembler::TrustedImm32(0x1f), Assembler::ScratchRegister);
+        as->rshift32(Assembler::ScratchRegister, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_shr32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        imm.m_value &= 0x1f;
+        as->rshift32(imm, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_ushr32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+        as->load32(addr, Assembler::ScratchRegister);
+        as->and32(Assembler::TrustedImm32(0x1f), Assembler::ScratchRegister);
+        as->urshift32(Assembler::ScratchRegister, reg);
+        return as->branchTest32(Assembler::Signed, reg, reg);
+    }
+
+    Assembler::Jump inline_ushr32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        imm.m_value &= 0x1f;
+        as->urshift32(imm, reg);
+        return as->branchTest32(Assembler::Signed, reg, reg);
+    }
+
+    Assembler::Jump inline_and32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        as->and32(addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        as->and32(Assembler::ScratchRegister, reg);
+#endif
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_and32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        as->and32(imm, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_or32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        as->or32(addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        as->or32(Assembler::ScratchRegister, reg);
+#endif
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_or32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        as->or32(imm, reg);
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_xor32(Assembler::Address addr, Assembler::RegisterID reg)
+    {
+#if HAVE(ALU_OPS_WITH_MEM_OPERAND)
+        as->xor32(addr, reg);
+#else
+        as->load32(addr, Assembler::ScratchRegister);
+        as->xor32(Assembler::ScratchRegister, reg);
+#endif
+        return Assembler::Jump();
+    }
+
+    Assembler::Jump inline_xor32(Assembler::TrustedImm32 imm, Assembler::RegisterID reg)
+    {
+        as->xor32(imm, reg);
+        return Assembler::Jump();
+    }
+
+
+
     Assembler *as;
     IR::AluOp op;
 };