V4 JIT: tune generated instructions for inplace binops

Generate better code for in-place binary operations where the right-hand
side is either a constant or a memory address. Now that the JIT can do
this, also tell the register allocator not to un-spill that right-hand
side.

Change-Id: I0ab852f6b92f90dfed99c05fbaf91aad2549ecf4
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>

1 files changed, 21 insertions, 2 deletions

diff --git a/src/qml/jit/qv4regalloc.cpp b/src/qml/jit/qv4regalloc.cpp
index 8ba3320c58..cccc07adde 100644
--- a/src/qml/jit/qv4regalloc.cpp
+++ b/src/qml/jit/qv4regalloc.cpp
@@ -649,16 +649,35 @@ protected: // IRDecoder
         } else {
             addUses(leftSource->asTemp(), Use::MustHaveRegister);
             addHint(target, leftSource->asTemp());
+            addHint(target, rightSource->asTemp());
 
-            addUses(rightSource->asTemp(), Use::MustHaveRegister);
+#if CPU(X86) || CPU(X86_64)
             switch (oper) {
+                // The rhs operand can be a memory address
             case OpAdd:
+            case OpSub:
             case OpMul:
-                addHint(target, rightSource->asTemp());
+            case OpDiv:
+#if CPU(X86_64)
+                if (leftSource->type == DoubleType || rightSource->type == DoubleType) {
+                    // well, on 64bit the doubles are mangled, so they must first be loaded in a register and demangled, so...:
+                    addUses(rightSource->asTemp(), Use::MustHaveRegister);
+                    break;
+                }
+#endif
+            case OpBitAnd:
+            case OpBitOr:
+            case OpBitXor:
+                addUses(rightSource->asTemp(), Use::CouldHaveRegister);
                 break;
+
             default:
+                addUses(rightSource->asTemp(), Use::MustHaveRegister);
                 break;
             }
+#else
+            addUses(rightSource->asTemp(), Use::MustHaveRegister);
+#endif
         }
     }