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| author | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-07-22 11:56:33 +0200 |
|---|---|---|
| committer | Erik Verbruggen <erik.verbruggen@digia.com> | 2014-08-12 12:30:34 +0200 |
| commit | 4ad1b63f257ac033e3876130f39eba3325363de5 (patch) | |
| tree | e617b30d8afa3ae0f132396fb70857e22cc6121f /src/qml/jit/qv4regalloc.cpp | |
| parent | f87d2a40ef2f20a11ed1353ed59ef8ced2cecb00 (diff) | |
V4 JIT: generate code for int32 comparisons.
Change-Id: I5e88fb3df7b01f4f515ce4d2e451a5a6f5ba92ad
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Diffstat (limited to 'src/qml/jit/qv4regalloc.cpp')
| -rw-r--r-- | src/qml/jit/qv4regalloc.cpp | 7 |
1 files changed, 2 insertions, 5 deletions
diff --git a/src/qml/jit/qv4regalloc.cpp b/src/qml/jit/qv4regalloc.cpp index cccc07adde..2192b8e60b 100644 --- a/src/qml/jit/qv4regalloc.cpp +++ b/src/qml/jit/qv4regalloc.cpp @@ -631,11 +631,8 @@ protected: // IRDecoder } } else if (oper == OpBitAnd || oper == OpBitOr || oper == OpBitXor || oper == OpLShift || oper == OpRShift || oper == OpURShift) { needsCall = false; - } else if (oper == OpAdd - || oper == OpMul - || - oper == OpSub - ) { + } else if (oper == OpAdd || oper == OpMul || oper == OpSub + || (oper >= OpGt && oper <= OpStrictNotEqual)) { if (leftSource->type == SInt32Type && rightSource->type == SInt32Type) needsCall = false; } |