diff options
| -rw-r--r-- | src/qml/compiler/qv4isel_masm.cpp | 15 | ||||
| -rw-r--r-- | src/qml/compiler/qv4regalloc.cpp | 3 |
2 files changed, 17 insertions, 1 deletions
diff --git a/src/qml/compiler/qv4isel_masm.cpp b/src/qml/compiler/qv4isel_masm.cpp index 6d69e57113..7d43066d3e 100644 --- a/src/qml/compiler/qv4isel_masm.cpp +++ b/src/qml/compiler/qv4isel_masm.cpp @@ -1213,7 +1213,20 @@ void InstructionSelection::unop(V4IR::AluOp oper, V4IR::Temp *sourceTemp, V4IR:: const char *opName = 0; switch (oper) { case V4IR::OpIfTrue: assert(!"unreachable"); break; - case V4IR::OpNot: setOp(op, opName, __qmljs_not); break; + case V4IR::OpNot: + if (sourceTemp->type == V4IR::BoolType && targetTemp->type == V4IR::BoolType) { + Assembler::RegisterID tReg = Assembler::ScratchRegister; + if (targetTemp->kind == V4IR::Temp::PhysicalRegister) + tReg = (Assembler::RegisterID) targetTemp->index; + _as->xor32(Assembler::TrustedImm32(0x1), + _as->toInt32Register(sourceTemp, Assembler::ScratchRegister), + tReg); + if (targetTemp->kind != V4IR::Temp::PhysicalRegister) + _as->storeBool(tReg, targetTemp); + return; + } else { + setOp(op, opName, __qmljs_not); break; + } case V4IR::OpUMinus: setOp(op, opName, __qmljs_uminus); break; case V4IR::OpUPlus: setOp(op, opName, __qmljs_uplus); break; case V4IR::OpCompl: setOp(op, opName, __qmljs_compl); break; diff --git a/src/qml/compiler/qv4regalloc.cpp b/src/qml/compiler/qv4regalloc.cpp index 926526c5fd..2c13a5fdd1 100644 --- a/src/qml/compiler/qv4regalloc.cpp +++ b/src/qml/compiler/qv4regalloc.cpp @@ -392,6 +392,9 @@ protected: // IRDecoder addDef(targetTemp); bool needsCall = true; + if (oper == OpNot && sourceTemp->type == V4IR::BoolType && targetTemp->type == V4IR::BoolType) + needsCall = false; + #if 0 // TODO: change masm to generate code switch (oper) { case OpIfTrue: |