diff options
-rw-r--r-- | src/qml/jit/qv4assembler.cpp | 2 | ||||
-rw-r--r-- | src/qml/jit/qv4assembler_p.h | 23 | ||||
-rw-r--r-- | src/qml/jit/qv4targetplatform_p.h | 28 |
3 files changed, 35 insertions, 18 deletions
diff --git a/src/qml/jit/qv4assembler.cpp b/src/qml/jit/qv4assembler.cpp index a2cb56abbe..ad8a5823e2 100644 --- a/src/qml/jit/qv4assembler.cpp +++ b/src/qml/jit/qv4assembler.cpp @@ -356,6 +356,8 @@ void Assembler<TargetConfiguration>::enterStandardStackFrame(const RegisterInfor slotAddr.offset -= RegisterSize; storePtr(regularRegistersToSave.at(i).reg<RegisterID>(), slotAddr); } + + platformFinishEnteringStandardStackFrame(this); } template <typename TargetConfiguration> diff --git a/src/qml/jit/qv4assembler_p.h b/src/qml/jit/qv4assembler_p.h index fd65c9b3d2..720c522e1d 100644 --- a/src/qml/jit/qv4assembler_p.h +++ b/src/qml/jit/qv4assembler_p.h @@ -387,32 +387,28 @@ struct RegisterSizeDependentAssembler<JITAssembler, MacroAssembler, TargetPlatfo static void loadDouble(JITAssembler *as, Address addr, FPRegisterID dest) { as->load64(addr, TargetPlatform::ReturnValueRegister); - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); as->move64ToDouble(TargetPlatform::ReturnValueRegister, dest); } static void storeDouble(JITAssembler *as, FPRegisterID source, Address addr) { as->moveDoubleTo64(source, TargetPlatform::ReturnValueRegister); - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); as->store64(TargetPlatform::ReturnValueRegister, addr); } static void storeDouble(JITAssembler *as, FPRegisterID source, IR::Expr* target) { as->moveDoubleTo64(source, TargetPlatform::ReturnValueRegister); - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); Pointer ptr = as->loadAddress(TargetPlatform::ScratchRegister, target); as->store64(TargetPlatform::ReturnValueRegister, ptr); } static void storeReturnValue(JITAssembler *as, FPRegisterID dest) { - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); as->move64ToDouble(TargetPlatform::ReturnValueRegister, dest); } @@ -427,16 +423,13 @@ struct RegisterSizeDependentAssembler<JITAssembler, MacroAssembler, TargetPlatfo if (t->type == IR::DoubleType) { as->moveDoubleTo64((FPRegisterID) t->index, TargetPlatform::ReturnValueRegister); - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), - TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); } else if (t->type == IR::UInt32Type) { RegisterID srcReg = (RegisterID) t->index; Jump intRange = as->branch32(RelationalCondition::GreaterThanOrEqual, srcReg, TrustedImm32(0)); as->convertUInt32ToDouble(srcReg, TargetPlatform::FPGpr0, TargetPlatform::ReturnValueRegister); as->moveDoubleTo64(TargetPlatform::FPGpr0, TargetPlatform::ReturnValueRegister); - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); Jump done = as->jump(); intRange.link(as); as->zeroExtend32ToPtr(srcReg, TargetPlatform::ReturnValueRegister); @@ -611,8 +604,7 @@ struct RegisterSizeDependentAssembler<JITAssembler, MacroAssembler, TargetPlatfo Jump fallback = as->branch32(RelationalCondition::GreaterThan, TargetPlatform::ScratchRegister, TrustedImm32(0)); // it's a double - as->move(TrustedImm64(QV4::Value::NaNEncodeMask), TargetPlatform::ScratchRegister); - as->xor64(TargetPlatform::ScratchRegister, TargetPlatform::ReturnValueRegister); + as->xor64(TargetPlatform::DoubleMaskRegister, TargetPlatform::ReturnValueRegister); as->move64ToDouble(TargetPlatform::ReturnValueRegister, TargetPlatform::FPGpr0); Jump success = as->branchTruncateDoubleToInt32(TargetPlatform::FPGpr0, TargetPlatform::ReturnValueRegister, @@ -718,6 +710,7 @@ public: using JITTargetPlatform::registerForArgument; using JITTargetPlatform::FPGpr0; using JITTargetPlatform::platformEnterStandardStackFrame; + using JITTargetPlatform::platformFinishEnteringStandardStackFrame; using JITTargetPlatform::platformLeaveStandardStackFrame; using RegisterSizeDependentOps = RegisterSizeDependentAssembler<Assembler<TargetConfiguration>, MacroAssembler, JITTargetPlatform, RegisterSize>; diff --git a/src/qml/jit/qv4targetplatform_p.h b/src/qml/jit/qv4targetplatform_p.h index fcc600eb2e..d9f8034b1f 100644 --- a/src/qml/jit/qv4targetplatform_p.h +++ b/src/qml/jit/qv4targetplatform_p.h @@ -55,6 +55,7 @@ #if ENABLE(ASSEMBLER) +#include <private/qv4value_p.h> #include "qv4registerinfo_p.h" #include <assembler/MacroAssembler.h> @@ -140,6 +141,7 @@ public: static const int StackShadowSpace = 0; static const int StackSpaceAllocatedUponFunctionEntry = RegisterSize; // Return address is pushed onto stack by the CPU. static void platformEnterStandardStackFrame(PlatformAssembler *as) { as->push(FramePointerRegister); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *) {} static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) @@ -194,6 +196,7 @@ public: static const RegisterID EngineRegister = JSC::X86Registers::r14; static const RegisterID ReturnValueRegister = JSC::X86Registers::eax; static const RegisterID ScratchRegister = JSC::X86Registers::r10; + static const RegisterID DoubleMaskRegister = JSC::X86Registers::r13; static const FPRegisterID FPGpr0 = JSC::X86Registers::xmm0; static const FPRegisterID FPGpr1 = JSC::X86Registers::xmm1; @@ -209,7 +212,7 @@ public: << RI(JSC::X86Registers::r8, QStringLiteral("r8"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) // r11 is used as scratch register by the macro assembler << RI(JSC::X86Registers::r12, QStringLiteral("r12"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) - << RI(JSC::X86Registers::r13, QStringLiteral("r13"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) + << RI(JSC::X86Registers::r13, QStringLiteral("r13"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::r14, QStringLiteral("r14"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::r15, QStringLiteral("r15"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::X86Registers::xmm2, QStringLiteral("xmm2"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) @@ -244,6 +247,10 @@ public: static const int StackShadowSpace = 0; static const int StackSpaceAllocatedUponFunctionEntry = RegisterSize; // Return address is pushed onto stack by the CPU. static void platformEnterStandardStackFrame(PlatformAssembler *as) { as->push(FramePointerRegister); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *as) + { + as->move(PlatformAssembler::TrustedImm64(QV4::Value::NaNEncodeMask), DoubleMaskRegister); + } static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) @@ -274,6 +281,7 @@ public: static const RegisterID EngineRegister = JSC::X86Registers::r14; static const RegisterID ReturnValueRegister = JSC::X86Registers::eax; static const RegisterID ScratchRegister = JSC::X86Registers::r10; + static const RegisterID DoubleMaskRegister = JSC::X86Registers::r13; static const FPRegisterID FPGpr0 = JSC::X86Registers::xmm0; static const FPRegisterID FPGpr1 = JSC::X86Registers::xmm1; @@ -289,7 +297,7 @@ public: << RI(JSC::X86Registers::r9, QStringLiteral("r9"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) // r11 is used as scratch register by the macro assembler << RI(JSC::X86Registers::r12, QStringLiteral("r12"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) - << RI(JSC::X86Registers::r13, QStringLiteral("r13"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) + << RI(JSC::X86Registers::r13, QStringLiteral("r13"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::r14, QStringLiteral("r14"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::r15, QStringLiteral("r15"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::X86Registers::xmm2, QStringLiteral("xmm2"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) @@ -322,6 +330,10 @@ public: static const int StackShadowSpace = 32; static const int StackSpaceAllocatedUponFunctionEntry = RegisterSize; // Return address is pushed onto stack by the CPU. static void platformEnterStandardStackFrame(PlatformAssembler *as) { as->push(FramePointerRegister); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *as) + { + as->move(PlatformAssembler::TrustedImm64(QV4::Value::NaNEncodeMask), DoubleMaskRegister); + } static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) @@ -440,6 +452,8 @@ public: as->push(FramePointerRegister); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *) {} + static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) { @@ -475,6 +489,7 @@ public: static const RegisterID ScratchRegister = JSC::ARM64Registers::x9; static const RegisterID EngineRegister = JSC::ARM64Registers::x27; static const RegisterID ReturnValueRegister = JSC::ARM64Registers::x0; + static const RegisterID DoubleMaskRegister = JSC::ARM64Registers::x26; static const FPRegisterID FPGpr0 = JSC::ARM64Registers::q0; static const FPRegisterID FPGpr1 = JSC::ARM64Registers::q1; @@ -505,7 +520,7 @@ public: << RI(JSC::ARM64Registers::x23, QStringLiteral("x23"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::ARM64Registers::x24, QStringLiteral("x24"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::ARM64Registers::x25, QStringLiteral("x25"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) - << RI(JSC::ARM64Registers::x26, QStringLiteral("x26"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) + << RI(JSC::ARM64Registers::x26, QStringLiteral("x26"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::ARM64Registers::x27, QStringLiteral("x27"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::ARM64Registers::x28, QStringLiteral("x28"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) @@ -572,6 +587,11 @@ public: as->pushPair(FramePointerRegister, JSC::ARM64Registers::lr); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *as) + { + as->move(PlatformAssembler::TrustedImm64(QV4::Value::NaNEncodeMask), DoubleMaskRegister); + } + static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) @@ -661,6 +681,8 @@ public: as->push(FramePointerRegister); } + static void platformFinishEnteringStandardStackFrame(PlatformAssembler *) {} + static void platformLeaveStandardStackFrame(PlatformAssembler *as, int frameSize) { if (frameSize > 0) |