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-rw-r--r--src/3rdparty/masm/assembler/AbstractMacroAssembler.h11
-rw-r--r--src/3rdparty/masm/assembler/MacroAssembler.h8
-rw-r--r--src/3rdparty/masm/assembler/MacroAssemblerSH4.cpp52
-rw-r--r--src/3rdparty/masm/assembler/MacroAssemblerSH4.h2293
-rw-r--r--src/3rdparty/masm/assembler/SH4Assembler.h2152
-rw-r--r--src/3rdparty/masm/wtf/Platform.h4
6 files changed, 0 insertions, 4520 deletions
diff --git a/src/3rdparty/masm/assembler/AbstractMacroAssembler.h b/src/3rdparty/masm/assembler/AbstractMacroAssembler.h
index 1076384900..d0c1c4613e 100644
--- a/src/3rdparty/masm/assembler/AbstractMacroAssembler.h
+++ b/src/3rdparty/masm/assembler/AbstractMacroAssembler.h
@@ -563,12 +563,6 @@ public:
{
ASSERT((type == ARM64Assembler::JumpTestBit) || (type == ARM64Assembler::JumpTestBitFixedSize));
}
-#elif CPU(SH4)
- Jump(AssemblerLabel jmp, SH4Assembler::JumpType type = SH4Assembler::JumpFar)
- : m_label(jmp)
- , m_type(type)
- {
- }
#else
Jump(AssemblerLabel jmp)
: m_label(jmp)
@@ -598,8 +592,6 @@ public:
masm->m_assembler.linkJump(m_label, masm->m_assembler.label(), m_type, m_condition, m_bitNumber, m_compareRegister);
else
masm->m_assembler.linkJump(m_label, masm->m_assembler.label(), m_type, m_condition);
-#elif CPU(SH4)
- masm->m_assembler.linkJump(m_label, masm->m_assembler.label(), m_type);
#else
masm->m_assembler.linkJump(m_label, masm->m_assembler.label());
#endif
@@ -640,9 +632,6 @@ public:
unsigned m_bitNumber;
ARM64Assembler::RegisterID m_compareRegister;
#endif
-#if CPU(SH4)
- SH4Assembler::JumpType m_type;
-#endif
};
#endif
diff --git a/src/3rdparty/masm/assembler/MacroAssembler.h b/src/3rdparty/masm/assembler/MacroAssembler.h
index 77aec128e5..99d0bff59d 100644
--- a/src/3rdparty/masm/assembler/MacroAssembler.h
+++ b/src/3rdparty/masm/assembler/MacroAssembler.h
@@ -57,12 +57,6 @@ namespace JSC { typedef MacroAssemblerX86 MacroAssemblerBase; };
#include "MacroAssemblerX86_64.h"
namespace JSC { typedef MacroAssemblerX86_64 MacroAssemblerBase; };
-#elif CPU(SH4)
-#include "MacroAssemblerSH4.h"
-namespace JSC {
-typedef MacroAssemblerSH4 MacroAssemblerBase;
-};
-
#else
#error "The MacroAssembler is not supported on this platform."
#endif
@@ -1497,8 +1491,6 @@ typedef MacroAssembler<MacroAssemblerMIPS> DefaultMacroAssembler;
typedef MacroAssembler<MacroAssemblerX86> DefaultMacroAssembler;
#elif CPU(X86_64)
typedef MacroAssembler<MacroAssemblerX86_64> DefaultMacroAssembler;
-#elif CPU(SH4)
-typedef JSC::MacroAssemblerSH4 DefaultMacroAssembler;
#endif
} // namespace JSC
diff --git a/src/3rdparty/masm/assembler/MacroAssemblerSH4.cpp b/src/3rdparty/masm/assembler/MacroAssemblerSH4.cpp
deleted file mode 100644
index 59de3ff48c..0000000000
--- a/src/3rdparty/masm/assembler/MacroAssemblerSH4.cpp
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2011 STMicroelectronics. All rights reserved.
- * Copyright (C) 2008 Apple Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "config.h"
-
-#if ENABLE(ASSEMBLER) && CPU(SH4)
-
-#include "MacroAssemblerSH4.h"
-
-namespace JSC {
-
-void MacroAssemblerSH4::linkCall(void* code, Call call, FunctionPtr function)
-{
- SH4Assembler::linkCall(code, call.m_label, function.value());
-}
-
-void MacroAssemblerSH4::repatchCall(CodeLocationCall call, CodeLocationLabel destination)
-{
- SH4Assembler::relinkCall(call.dataLocation(), destination.executableAddress());
-}
-
-void MacroAssemblerSH4::repatchCall(CodeLocationCall call, FunctionPtr destination)
-{
- SH4Assembler::relinkCall(call.dataLocation(), destination.executableAddress());
-}
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER)
diff --git a/src/3rdparty/masm/assembler/MacroAssemblerSH4.h b/src/3rdparty/masm/assembler/MacroAssemblerSH4.h
deleted file mode 100644
index 1e5a3113bb..0000000000
--- a/src/3rdparty/masm/assembler/MacroAssemblerSH4.h
+++ /dev/null
@@ -1,2293 +0,0 @@
-/*
- * Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.
- * Copyright (C) 2008 Apple Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#ifndef MacroAssemblerSH4_h
-#define MacroAssemblerSH4_h
-
-#if ENABLE(ASSEMBLER) && CPU(SH4)
-
-#include "SH4Assembler.h"
-#include "AbstractMacroAssembler.h"
-#include <wtf/Assertions.h>
-
-namespace JSC {
-
-class MacroAssemblerSH4 : public AbstractMacroAssembler<SH4Assembler> {
-public:
- typedef SH4Assembler::FPRegisterID FPRegisterID;
-
- static const Scale ScalePtr = TimesFour;
- static const FPRegisterID fscratch = SH4Registers::fr10;
- static const RegisterID stackPointerRegister = SH4Registers::sp;
- static const RegisterID linkRegister = SH4Registers::pr;
- static const RegisterID scratchReg3 = SH4Registers::r13;
-
- static const int MaximumCompactPtrAlignedAddressOffset = 60;
-
- static bool isCompactPtrAlignedAddressOffset(ptrdiff_t value)
- {
- return (value >= 0) && (value <= MaximumCompactPtrAlignedAddressOffset);
- }
-
- enum RelationalCondition {
- Equal = SH4Assembler::EQ,
- NotEqual = SH4Assembler::NE,
- Above = SH4Assembler::HI,
- AboveOrEqual = SH4Assembler::HS,
- Below = SH4Assembler::LI,
- BelowOrEqual = SH4Assembler::LS,
- GreaterThan = SH4Assembler::GT,
- GreaterThanOrEqual = SH4Assembler::GE,
- LessThan = SH4Assembler::LT,
- LessThanOrEqual = SH4Assembler::LE
- };
-
- enum ResultCondition {
- Overflow = SH4Assembler::OF,
- Signed = SH4Assembler::SI,
- Zero = SH4Assembler::EQ,
- NonZero = SH4Assembler::NE
- };
-
- enum DoubleCondition {
- // These conditions will only evaluate to true if the comparison is ordered - i.e. neither operand is NaN.
- DoubleEqual = SH4Assembler::EQ,
- DoubleNotEqual = SH4Assembler::NE,
- DoubleGreaterThan = SH4Assembler::GT,
- DoubleGreaterThanOrEqual = SH4Assembler::GE,
- DoubleLessThan = SH4Assembler::LT,
- DoubleLessThanOrEqual = SH4Assembler::LE,
- // If either operand is NaN, these conditions always evaluate to true.
- DoubleEqualOrUnordered = SH4Assembler::EQU,
- DoubleNotEqualOrUnordered = SH4Assembler::NEU,
- DoubleGreaterThanOrUnordered = SH4Assembler::GTU,
- DoubleGreaterThanOrEqualOrUnordered = SH4Assembler::GEU,
- DoubleLessThanOrUnordered = SH4Assembler::LTU,
- DoubleLessThanOrEqualOrUnordered = SH4Assembler::LEU,
- };
-
- RegisterID claimScratch()
- {
- return m_assembler.claimScratch();
- }
-
- void releaseScratch(RegisterID reg)
- {
- m_assembler.releaseScratch(reg);
- }
-
- // Integer arithmetic operations
-
- void add32(RegisterID src, RegisterID dest)
- {
- m_assembler.addlRegReg(src, dest);
- }
-
- void add32(TrustedImm32 imm, RegisterID dest)
- {
- if (m_assembler.isImmediate(imm.m_value)) {
- m_assembler.addlImm8r(imm.m_value, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm.m_value, scr);
- m_assembler.addlRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void add32(TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- if (src != dest)
- m_assembler.movlRegReg(src, dest);
- add32(imm, dest);
- }
-
- void add32(TrustedImm32 imm, Address address)
- {
- RegisterID scr = claimScratch();
- load32(address, scr);
- add32(imm, scr);
- store32(scr, address);
- releaseScratch(scr);
- }
-
- void add32(Address src, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- load32(src, scr);
- m_assembler.addlRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void add32(AbsoluteAddress src, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- load32(src.m_ptr, scr);
- m_assembler.addlRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void and32(RegisterID src, RegisterID dest)
- {
- m_assembler.andlRegReg(src, dest);
- }
-
- void and32(TrustedImm32 imm, RegisterID dest)
- {
- if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) {
- m_assembler.andlImm8r(imm.m_value, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- m_assembler.andlRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void and32(TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- if (src != dest) {
- move(imm, dest);
- and32(src, dest);
- return;
- }
-
- and32(imm, dest);
- }
-
- void lshift32(RegisterID shiftamount, RegisterID dest)
- {
- if (shiftamount == SH4Registers::r0)
- m_assembler.andlImm8r(0x1f, shiftamount);
- else {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x1f, scr);
- m_assembler.andlRegReg(scr, shiftamount);
- releaseScratch(scr);
- }
- m_assembler.shllRegReg(dest, shiftamount);
- }
-
- void rshift32(int imm, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(-imm, scr);
- m_assembler.shaRegReg(dest, scr);
- releaseScratch(scr);
- }
-
- void lshift32(TrustedImm32 imm, RegisterID dest)
- {
- if (!imm.m_value)
- return;
-
- if ((imm.m_value == 1) || (imm.m_value == 2) || (imm.m_value == 8) || (imm.m_value == 16)) {
- m_assembler.shllImm8r(imm.m_value, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((imm.m_value & 0x1f) , scr);
- m_assembler.shllRegReg(dest, scr);
- releaseScratch(scr);
- }
-
- void lshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest)
- {
- if (src != dest)
- move(src, dest);
-
- lshift32(shiftamount, dest);
- }
-
- void mul32(RegisterID src, RegisterID dest)
- {
- m_assembler.imullRegReg(src, dest);
- m_assembler.stsmacl(dest);
- }
-
- void mul32(TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- move(imm, scr);
- if (src != dest)
- move(src, dest);
- mul32(scr, dest);
- releaseScratch(scr);
- }
-
- void or32(RegisterID src, RegisterID dest)
- {
- m_assembler.orlRegReg(src, dest);
- }
-
- void or32(TrustedImm32 imm, RegisterID dest)
- {
- if ((imm.m_value <= 255) && (imm.m_value >= 0) && (dest == SH4Registers::r0)) {
- m_assembler.orlImm8r(imm.m_value, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm.m_value, scr);
- m_assembler.orlRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void or32(RegisterID op1, RegisterID op2, RegisterID dest)
- {
- if (op1 == op2)
- move(op1, dest);
- else if (op1 == dest)
- or32(op2, dest);
- else {
- move(op2, dest);
- or32(op1, dest);
- }
- }
-
-
-void or32(TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- if (src != dest) {
- move(imm, dest);
- or32(src, dest);
- return;
- }
-
- or32(imm, dest);
- }
-
- void xor32(TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- if (src != dest) {
- move(imm, dest);
- xor32(src, dest);
- return;
- }
-
- xor32(imm, dest);
- }
-
- void rshift32(RegisterID shiftamount, RegisterID dest)
- {
- if (shiftamount == SH4Registers::r0)
- m_assembler.andlImm8r(0x1f, shiftamount);
- else {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x1f, scr);
- m_assembler.andlRegReg(scr, shiftamount);
- releaseScratch(scr);
- }
- m_assembler.neg(shiftamount, shiftamount);
- m_assembler.shaRegReg(dest, shiftamount);
- }
-
- void rshift32(TrustedImm32 imm, RegisterID dest)
- {
- if (imm.m_value & 0x1f)
- rshift32(imm.m_value & 0x1f, dest);
- }
-
- void rshift32(RegisterID src, TrustedImm32 imm, RegisterID dest)
- {
- if (src != dest)
- move(src, dest);
- rshift32(imm, dest);
- }
-
- void sub32(RegisterID src, RegisterID dest)
- {
- m_assembler.sublRegReg(src, dest);
- }
-
- void sub32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg)
- {
- RegisterID result = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
-
- if (m_assembler.isImmediate(-imm.m_value))
- m_assembler.addlImm8r(-imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.sublRegReg(scratchReg3, result);
- }
-
- store32(result, scratchReg);
- releaseScratch(result);
- }
-
- void sub32(TrustedImm32 imm, AbsoluteAddress address)
- {
- RegisterID result = claimScratch();
- RegisterID scratchReg = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
-
- if (m_assembler.isImmediate(-imm.m_value))
- m_assembler.addlImm8r(-imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.sublRegReg(scratchReg3, result);
- }
-
- store32(result, scratchReg);
- releaseScratch(result);
- releaseScratch(scratchReg);
- }
-
- void add32(TrustedImm32 imm, AbsoluteAddress address, RegisterID scratchReg)
- {
- RegisterID result = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
-
- if (m_assembler.isImmediate(imm.m_value))
- m_assembler.addlImm8r(imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.addlRegReg(scratchReg3, result);
- }
-
- store32(result, scratchReg);
- releaseScratch(result);
- }
-
- void add32(TrustedImm32 imm, AbsoluteAddress address)
- {
- RegisterID result = claimScratch();
- RegisterID scratchReg = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scratchReg);
- m_assembler.movlMemReg(scratchReg, result);
-
- if (m_assembler.isImmediate(imm.m_value))
- m_assembler.addlImm8r(imm.m_value, result);
- else {
- m_assembler.loadConstant(imm.m_value, scratchReg3);
- m_assembler.addlRegReg(scratchReg3, result);
- }
-
- store32(result, scratchReg);
- releaseScratch(result);
- releaseScratch(scratchReg);
- }
-
- void add64(TrustedImm32 imm, AbsoluteAddress address)
- {
- RegisterID scr1 = claimScratch();
- RegisterID scr2 = claimScratch();
-
- // Add 32-bit LSB first.
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scr1);
- m_assembler.movlMemReg(scr1, scr1); // scr1 = 32-bit LSB of int64 @ address
- m_assembler.loadConstant(imm.m_value, scr2);
- m_assembler.clrt();
- m_assembler.addclRegReg(scr1, scr2);
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr), scr1);
- m_assembler.movlRegMem(scr2, scr1); // Update address with 32-bit LSB result.
-
- // Then add 32-bit MSB.
- m_assembler.addlImm8r(4, scr1);
- m_assembler.movlMemReg(scr1, scr1); // scr1 = 32-bit MSB of int64 @ address
- m_assembler.movt(scr2);
- if (imm.m_value < 0)
- m_assembler.addlImm8r(-1, scr2); // Sign extend imm value if needed.
- m_assembler.addvlRegReg(scr2, scr1);
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address.m_ptr) + 4, scr2);
- m_assembler.movlRegMem(scr1, scr2); // Update (address + 4) with 32-bit MSB result.
-
- releaseScratch(scr2);
- releaseScratch(scr1);
- }
-
- void sub32(TrustedImm32 imm, RegisterID dest)
- {
- if (m_assembler.isImmediate(-imm.m_value)) {
- m_assembler.addlImm8r(-imm.m_value, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm.m_value, scr);
- m_assembler.sublRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void sub32(Address src, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- load32(src, scr);
- m_assembler.sublRegReg(scr, dest);
- releaseScratch(scr);
- }
-
- void xor32(RegisterID src, RegisterID dest)
- {
- m_assembler.xorlRegReg(src, dest);
- }
-
- void xor32(TrustedImm32 imm, RegisterID srcDest)
- {
- if (imm.m_value == -1) {
- m_assembler.notlReg(srcDest, srcDest);
- return;
- }
-
- if ((srcDest != SH4Registers::r0) || (imm.m_value > 255) || (imm.m_value < 0)) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- m_assembler.xorlRegReg(scr, srcDest);
- releaseScratch(scr);
- return;
- }
-
- m_assembler.xorlImm8r(imm.m_value, srcDest);
- }
-
- void compare32(int imm, RegisterID dst, RelationalCondition cond)
- {
- if (((cond == Equal) || (cond == NotEqual)) && (dst == SH4Registers::r0) && m_assembler.isImmediate(imm)) {
- m_assembler.cmpEqImmR0(imm, dst);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm, scr);
- m_assembler.cmplRegReg(scr, dst, SH4Condition(cond));
- releaseScratch(scr);
- }
-
- void compare32(int offset, RegisterID base, RegisterID left, RelationalCondition cond)
- {
- RegisterID scr = claimScratch();
- if (!offset) {
- m_assembler.movlMemReg(base, scr);
- m_assembler.cmplRegReg(scr, left, SH4Condition(cond));
- releaseScratch(scr);
- return;
- }
-
- if ((offset < 0) || (offset >= 64)) {
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- m_assembler.cmplRegReg(scr, left, SH4Condition(cond));
- releaseScratch(scr);
- return;
- }
-
- m_assembler.movlMemReg(offset >> 2, base, scr);
- m_assembler.cmplRegReg(scr, left, SH4Condition(cond));
- releaseScratch(scr);
- }
-
- void testImm(int imm, int offset, RegisterID base)
- {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
-
- if ((offset < 0) || (offset >= 64)) {
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- } else if (offset)
- m_assembler.movlMemReg(offset >> 2, base, scr);
- else
- m_assembler.movlMemReg(base, scr);
- if (m_assembler.isImmediate(imm))
- m_assembler.movImm8(imm, scr1);
- else
- m_assembler.loadConstant(imm, scr1);
-
- m_assembler.testlRegReg(scr, scr1);
- releaseScratch(scr);
- releaseScratch(scr1);
- }
-
- void testlImm(int imm, RegisterID dst)
- {
- if ((dst == SH4Registers::r0) && (imm <= 255) && (imm >= 0)) {
- m_assembler.testlImm8r(imm, dst);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm, scr);
- m_assembler.testlRegReg(scr, dst);
- releaseScratch(scr);
- }
-
- void compare32(RegisterID right, int offset, RegisterID base, RelationalCondition cond)
- {
- if (!offset) {
- RegisterID scr = claimScratch();
- m_assembler.movlMemReg(base, scr);
- m_assembler.cmplRegReg(right, scr, SH4Condition(cond));
- releaseScratch(scr);
- return;
- }
-
- if ((offset < 0) || (offset >= 64)) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- m_assembler.cmplRegReg(right, scr, SH4Condition(cond));
- releaseScratch(scr);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.movlMemReg(offset >> 2, base, scr);
- m_assembler.cmplRegReg(right, scr, SH4Condition(cond));
- releaseScratch(scr);
- }
-
- void compare32(int imm, int offset, RegisterID base, RelationalCondition cond)
- {
- if (!offset) {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.movlMemReg(base, scr);
- m_assembler.loadConstant(imm, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr1);
- releaseScratch(scr);
- return;
- }
-
- if ((offset < 0) || (offset >= 64)) {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant(offset, scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, scr);
- m_assembler.loadConstant(imm, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr1);
- releaseScratch(scr);
- return;
- }
-
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.movlMemReg(offset >> 2, base, scr);
- m_assembler.loadConstant(imm, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr1);
- releaseScratch(scr);
- }
-
- // Memory access operation
-
- void load32(ImplicitAddress address, RegisterID dest)
- {
- load32(address.base, address.offset, dest);
- }
-
- void load8(ImplicitAddress address, RegisterID dest)
- {
- load8(address.base, address.offset, dest);
- }
-
- void load8(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- load8(scr, address.offset, dest);
- releaseScratch(scr);
- }
-
- void load8Signed(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- load8Signed(scr, address.offset, dest);
- releaseScratch(scr);
- }
-
- void load32(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- load32(scr, address.offset, dest);
- releaseScratch(scr);
- }
-
- void load32(const void* address, RegisterID dest)
- {
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(const_cast<void*>(address)), dest);
- m_assembler.movlMemReg(dest, dest);
- }
-
- void load32(RegisterID base, int offset, RegisterID dest)
- {
- if (!offset) {
- m_assembler.movlMemReg(base, dest);
- return;
- }
-
- if ((offset >= 0) && (offset < 64)) {
- m_assembler.movlMemReg(offset >> 2, base, dest);
- return;
- }
-
- if ((dest == SH4Registers::r0) && (dest != base)) {
- m_assembler.loadConstant((offset), dest);
- m_assembler.movlR0mr(base, dest);
- return;
- }
-
- RegisterID scr;
- if (dest == base)
- scr = claimScratch();
- else
- scr = dest;
- m_assembler.loadConstant((offset), scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlMemReg(scr, dest);
-
- if (dest == base)
- releaseScratch(scr);
- }
-
- void load8Signed(RegisterID base, int offset, RegisterID dest)
- {
- if (!offset) {
- m_assembler.movbMemReg(base, dest);
- return;
- }
-
- if ((offset > 0) && (offset < 64) && (dest == SH4Registers::r0)) {
- m_assembler.movbMemReg(offset, base, dest);
- return;
- }
-
- if (base != dest) {
- m_assembler.loadConstant((offset), dest);
- m_assembler.addlRegReg(base, dest);
- m_assembler.movbMemReg(dest, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((offset), scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movbMemReg(scr, dest);
- releaseScratch(scr);
- }
-
- void load8(RegisterID base, int offset, RegisterID dest)
- {
- if (!offset) {
- m_assembler.movbMemReg(base, dest);
- m_assembler.extub(dest, dest);
- return;
- }
-
- if ((offset > 0) && (offset < 64) && (dest == SH4Registers::r0)) {
- m_assembler.movbMemReg(offset, base, dest);
- m_assembler.extub(dest, dest);
- return;
- }
-
- if (base != dest) {
- m_assembler.loadConstant((offset), dest);
- m_assembler.addlRegReg(base, dest);
- m_assembler.movbMemReg(dest, dest);
- m_assembler.extub(dest, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((offset), scr);
- m_assembler.addlRegReg(base, scr);
- m_assembler.movbMemReg(scr, dest);
- m_assembler.extub(dest, dest);
- releaseScratch(scr);
- }
-
- void load32(RegisterID r0, RegisterID src, RegisterID dst)
- {
- ASSERT(r0 == SH4Registers::r0);
- m_assembler.movlR0mr(src, dst);
- }
-
- void load32(RegisterID src, RegisterID dst)
- {
- m_assembler.movlMemReg(src, dst);
- }
-
- void load16(ImplicitAddress address, RegisterID dest)
- {
- if (!address.offset) {
- m_assembler.movwMemReg(address.base, dest);
- extuw(dest, dest);
- return;
- }
-
- if ((address.offset > 0) && (address.offset < 64) && (dest == SH4Registers::r0)) {
- m_assembler.movwMemReg(address.offset, address.base, dest);
- extuw(dest, dest);
- return;
- }
-
- if (address.base != dest) {
- m_assembler.loadConstant((address.offset), dest);
- m_assembler.addlRegReg(address.base, dest);
- m_assembler.movwMemReg(dest, dest);
- extuw(dest, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- m_assembler.loadConstant((address.offset), scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movwMemReg(scr, dest);
- extuw(dest, dest);
- releaseScratch(scr);
- }
-
- void load16Unaligned(BaseIndex address, RegisterID dest)
- {
-
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
-
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- add32(address.base, scr);
- load8(scr, scr1);
- add32(TrustedImm32(1), scr);
- load8(scr, dest);
- m_assembler.shllImm8r(8, dest);
- or32(scr1, dest);
-
- releaseScratch(scr);
- releaseScratch(scr1);
- }
-
- void load16(RegisterID src, RegisterID dest)
- {
- m_assembler.movwMemReg(src, dest);
- extuw(dest, dest);
- }
-
- void load16Signed(RegisterID src, RegisterID dest)
- {
- m_assembler.movwMemReg(src, dest);
- }
-
- void load16(RegisterID r0, RegisterID src, RegisterID dest)
- {
- ASSERT(r0 == SH4Registers::r0);
- m_assembler.movwR0mr(src, dest);
- extuw(dest, dest);
- }
-
- void load16Signed(RegisterID r0, RegisterID src, RegisterID dest)
- {
- ASSERT(r0 == SH4Registers::r0);
- m_assembler.movwR0mr(src, dest);
- }
-
- void load16(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
-
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
- if (address.base == SH4Registers::r0)
- load16(address.base, scr, dest);
- else {
- add32(address.base, scr);
- load16(scr, dest);
- }
-
- releaseScratch(scr);
- }
-
- void load16Signed(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
-
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
- if (address.base == SH4Registers::r0)
- load16Signed(address.base, scr, dest);
- else {
- add32(address.base, scr);
- load16Signed(scr, dest);
- }
-
- releaseScratch(scr);
- }
-
- void store8(RegisterID src, BaseIndex address)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
-
- m_assembler.movbRegMem(src, scr);
-
- releaseScratch(scr);
- }
-
- void store16(RegisterID src, BaseIndex address)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
-
- m_assembler.movwRegMem(src, scr);
-
- releaseScratch(scr);
- }
-
- void store32(RegisterID src, ImplicitAddress address)
- {
- RegisterID scr = claimScratch();
- store32(src, address.offset, address.base, scr);
- releaseScratch(scr);
- }
-
- void store32(RegisterID src, int offset, RegisterID base, RegisterID scr)
- {
- if (!offset) {
- m_assembler.movlRegMem(src, base);
- return;
- }
-
- if ((offset >=0) && (offset < 64)) {
- m_assembler.movlRegMem(src, offset >> 2, base);
- return;
- }
-
- m_assembler.loadConstant((offset), scr);
- if (scr == SH4Registers::r0) {
- m_assembler.movlRegMemr0(src, base);
- return;
- }
-
- m_assembler.addlRegReg(base, scr);
- m_assembler.movlRegMem(src, scr);
- }
-
- void store32(RegisterID src, RegisterID offset, RegisterID base)
- {
- ASSERT(offset == SH4Registers::r0);
- m_assembler.movlRegMemr0(src, base);
- }
-
- void store32(RegisterID src, RegisterID dst)
- {
- m_assembler.movlRegMem(src, dst);
- }
-
- void store32(TrustedImm32 imm, ImplicitAddress address)
- {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- store32(scr, address.offset, address.base, scr1);
- releaseScratch(scr);
- releaseScratch(scr1);
- }
-
- void store32(RegisterID src, BaseIndex address)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- store32(src, Address(scr, address.offset));
-
- releaseScratch(scr);
- }
-
- void store32(TrustedImm32 imm, void* address)
- {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant((imm.m_value), scr);
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr1);
- m_assembler.movlRegMem(scr, scr1);
- releaseScratch(scr);
- releaseScratch(scr1);
- }
-
- void store32(RegisterID src, void* address)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);
- m_assembler.movlRegMem(src, scr);
- releaseScratch(scr);
- }
-
- DataLabel32 load32WithAddressOffsetPatch(Address address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- DataLabel32 label(this);
- m_assembler.loadConstantUnReusable(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, dest);
- releaseScratch(scr);
- return label;
- }
-
- DataLabel32 store32WithAddressOffsetPatch(RegisterID src, Address address)
- {
- RegisterID scr = claimScratch();
- DataLabel32 label(this);
- m_assembler.loadConstantUnReusable(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlRegMem(src, scr);
- releaseScratch(scr);
- return label;
- }
-
- DataLabelCompact load32WithCompactAddressOffsetPatch(Address address, RegisterID dest)
- {
- DataLabelCompact dataLabel(this);
- ASSERT(address.offset <= MaximumCompactPtrAlignedAddressOffset);
- ASSERT(address.offset >= 0);
- m_assembler.movlMemRegCompact(address.offset >> 2, address.base, dest);
- return dataLabel;
- }
-
- ConvertibleLoadLabel convertibleLoadPtr(Address address, RegisterID dest)
- {
- ConvertibleLoadLabel result(this);
-
- RegisterID scr = claimScratch();
- m_assembler.movImm8(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, dest);
- releaseScratch(scr);
-
- return result;
- }
-
- // Floating-point operations
-
- static bool supportsFloatingPoint() { return true; }
- static bool supportsFloatingPointTruncate() { return true; }
- static bool supportsFloatingPointSqrt() { return true; }
- static bool supportsFloatingPointAbs() { return false; }
-
- void moveDoubleToInts(FPRegisterID src, RegisterID dest1, RegisterID dest2)
- {
- m_assembler.fldsfpul((FPRegisterID)(src + 1));
- m_assembler.stsfpulReg(dest1);
- m_assembler.fldsfpul(src);
- m_assembler.stsfpulReg(dest2);
- }
-
- void moveIntsToDouble(RegisterID src1, RegisterID src2, FPRegisterID dest, FPRegisterID scratch)
- {
- UNUSED_PARAM(scratch);
- m_assembler.ldsrmfpul(src1);
- m_assembler.fstsfpul((FPRegisterID)(dest + 1));
- m_assembler.ldsrmfpul(src2);
- m_assembler.fstsfpul(dest);
- }
-
- void loadFloat(BaseIndex address, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- m_assembler.fmovsReadrm(scr, dest);
- releaseScratch(scr);
- }
-
- void loadDouble(BaseIndex address, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1));
- m_assembler.fmovsReadrm(scr, dest);
- releaseScratch(scr);
- }
-
- void loadDouble(ImplicitAddress address, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
-
- m_assembler.loadConstant(address.offset, scr);
- if (address.base == SH4Registers::r0) {
- m_assembler.fmovsReadr0r(scr, (FPRegisterID)(dest + 1));
- m_assembler.addlImm8r(4, scr);
- m_assembler.fmovsReadr0r(scr, dest);
- releaseScratch(scr);
- return;
- }
-
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1));
- m_assembler.fmovsReadrm(scr, dest);
- releaseScratch(scr);
- }
-
- void loadDouble(const void* address, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(address), scr);
- m_assembler.fmovsReadrminc(scr, (FPRegisterID)(dest + 1));
- m_assembler.fmovsReadrm(scr, dest);
- releaseScratch(scr);
- }
-
- void storeFloat(FPRegisterID src, BaseIndex address)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- m_assembler.fmovsWriterm(src, scr);
-
- releaseScratch(scr);
- }
-
- void storeDouble(FPRegisterID src, ImplicitAddress address)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.fmovsWriterm((FPRegisterID)(src + 1), scr);
- m_assembler.addlImm8r(4, scr);
- m_assembler.fmovsWriterm(src, scr);
- releaseScratch(scr);
- }
-
- void storeDouble(FPRegisterID src, BaseIndex address)
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- m_assembler.fmovsWriterm((FPRegisterID)(src + 1), scr);
- m_assembler.addlImm8r(4, scr);
- m_assembler.fmovsWriterm(src, scr);
-
- releaseScratch(scr);
- }
-
- void addDouble(FPRegisterID op1, FPRegisterID op2, FPRegisterID dest)
- {
- if (op1 == dest)
- m_assembler.daddRegReg(op2, dest);
- else {
- m_assembler.dmovRegReg(op1, dest);
- m_assembler.daddRegReg(op2, dest);
- }
- }
-
- void addDouble(FPRegisterID src, FPRegisterID dest)
- {
- m_assembler.daddRegReg(src, dest);
- }
-
- void addDouble(AbsoluteAddress address, FPRegisterID dest)
- {
- loadDouble(address.m_ptr, fscratch);
- addDouble(fscratch, dest);
- }
-
- void addDouble(Address address, FPRegisterID dest)
- {
- loadDouble(address, fscratch);
- addDouble(fscratch, dest);
- }
-
- void subDouble(FPRegisterID src, FPRegisterID dest)
- {
- m_assembler.dsubRegReg(src, dest);
- }
-
- void subDouble(Address address, FPRegisterID dest)
- {
- loadDouble(address, fscratch);
- subDouble(fscratch, dest);
- }
-
- void mulDouble(FPRegisterID src, FPRegisterID dest)
- {
- m_assembler.dmulRegReg(src, dest);
- }
-
- void mulDouble(Address address, FPRegisterID dest)
- {
- loadDouble(address, fscratch);
- mulDouble(fscratch, dest);
- }
-
- void divDouble(FPRegisterID src, FPRegisterID dest)
- {
- m_assembler.ddivRegReg(src, dest);
- }
-
- void convertFloatToDouble(FPRegisterID src, FPRegisterID dst)
- {
- m_assembler.fldsfpul(src);
- m_assembler.dcnvsd(dst);
- }
-
- void convertDoubleToFloat(FPRegisterID src, FPRegisterID dst)
- {
- m_assembler.dcnvds(src);
- m_assembler.fstsfpul(dst);
- }
-
- void convertInt32ToDouble(RegisterID src, FPRegisterID dest)
- {
- m_assembler.ldsrmfpul(src);
- m_assembler.floatfpulDreg(dest);
- }
-
- void convertInt32ToDouble(AbsoluteAddress src, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(src.m_ptr), scr);
- convertInt32ToDouble(scr, dest);
- releaseScratch(scr);
- }
-
- void convertInt32ToDouble(Address src, FPRegisterID dest)
- {
- RegisterID scr = claimScratch();
- load32(src, scr);
- convertInt32ToDouble(scr, dest);
- releaseScratch(scr);
- }
-
- void load32WithUnalignedHalfWords(BaseIndex address, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- RegisterID scr1 = claimScratch();
- Jump m_jump;
- JumpList end;
-
- if (dest != SH4Registers::r0)
- move(SH4Registers::r0, scr1);
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
-
- if (address.offset)
- add32(TrustedImm32(address.offset), scr);
-
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 68, sizeof(uint32_t));
- move(scr, SH4Registers::r0);
- m_assembler.andlImm8r(0x3, SH4Registers::r0);
- m_assembler.cmpEqImmR0(0x0, SH4Registers::r0);
- m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
- if (dest != SH4Registers::r0)
- move(scr1, SH4Registers::r0);
-
- load32(scr, dest);
- end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
- m_assembler.nop();
- m_jump.link(this);
- m_assembler.andlImm8r(0x1, SH4Registers::r0);
- m_assembler.cmpEqImmR0(0x0, SH4Registers::r0);
-
- if (dest != SH4Registers::r0)
- move(scr1, SH4Registers::r0);
-
- m_jump = Jump(m_assembler.jne(), SH4Assembler::JumpNear);
- load16(scr, scr1);
- add32(TrustedImm32(2), scr);
- load16(scr, dest);
- m_assembler.shllImm8r(16, dest);
- or32(scr1, dest);
- end.append(Jump(m_assembler.bra(), SH4Assembler::JumpNear));
- m_assembler.nop();
- m_jump.link(this);
- load8(scr, scr1);
- add32(TrustedImm32(1), scr);
- load16(scr, dest);
- m_assembler.shllImm8r(8, dest);
- or32(dest, scr1);
- add32(TrustedImm32(2), scr);
- load8(scr, dest);
- m_assembler.shllImm8r(8, dest);
- m_assembler.shllImm8r(16, dest);
- or32(scr1, dest);
- end.link(this);
-
- releaseScratch(scr);
- releaseScratch(scr1);
- }
-
- Jump branch32WithUnalignedHalfWords(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
- {
- RegisterID scr = scratchReg3;
- load32WithUnalignedHalfWords(left, scr);
- if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
- m_assembler.testlRegReg(scr, scr);
- else
- compare32(right.m_value, scr, cond);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchDoubleNonZero(FPRegisterID reg, FPRegisterID scratch)
- {
- m_assembler.movImm8(0, scratchReg3);
- convertInt32ToDouble(scratchReg3, scratch);
- return branchDouble(DoubleNotEqual, reg, scratch);
- }
-
- Jump branchDoubleZeroOrNaN(FPRegisterID reg, FPRegisterID scratch)
- {
- m_assembler.movImm8(0, scratchReg3);
- convertInt32ToDouble(scratchReg3, scratch);
- return branchDouble(DoubleEqualOrUnordered, reg, scratch);
- }
-
- Jump branchDouble(DoubleCondition cond, FPRegisterID left, FPRegisterID right)
- {
- if (cond == DoubleEqual) {
- m_assembler.dcmppeq(right, left);
- return branchTrue();
- }
-
- if (cond == DoubleNotEqual) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppeq(right, left);
- releaseScratch(scr);
- Jump m_jump = branchFalse();
- end.link(this);
- return m_jump;
- }
-
- if (cond == DoubleGreaterThan) {
- m_assembler.dcmppgt(right, left);
- return branchTrue();
- }
-
- if (cond == DoubleGreaterThanOrEqual) {
- m_assembler.dcmppgt(left, right);
- return branchFalse();
- }
-
- if (cond == DoubleLessThan) {
- m_assembler.dcmppgt(left, right);
- return branchTrue();
- }
-
- if (cond == DoubleLessThanOrEqual) {
- m_assembler.dcmppgt(right, left);
- return branchFalse();
- }
-
- if (cond == DoubleEqualOrUnordered) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppeq(left, right);
- Jump m_jump = Jump(m_assembler.je());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- if (cond == DoubleGreaterThanOrUnordered) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppgt(right, left);
- Jump m_jump = Jump(m_assembler.je());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- if (cond == DoubleGreaterThanOrEqualOrUnordered) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppgt(left, right);
- Jump m_jump = Jump(m_assembler.jne());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- if (cond == DoubleLessThanOrUnordered) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppgt(left, right);
- Jump m_jump = Jump(m_assembler.je());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- if (cond == DoubleLessThanOrEqualOrUnordered) {
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppgt(right, left);
- Jump m_jump = Jump(m_assembler.jne());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- ASSERT(cond == DoubleNotEqualOrUnordered);
- RegisterID scr = claimScratch();
- JumpList end;
- m_assembler.loadConstant(0x7fbfffff, scratchReg3);
- m_assembler.dcnvds(right);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 22, sizeof(uint32_t));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcnvds(left);
- m_assembler.stsfpulReg(scr);
- m_assembler.cmplRegReg(scratchReg3, scr, SH4Condition(Equal));
- end.append(Jump(m_assembler.je(), SH4Assembler::JumpNear));
- m_assembler.dcmppeq(right, left);
- Jump m_jump = Jump(m_assembler.jne());
- end.link(this);
- m_assembler.extraInstrForBranch(scr);
- releaseScratch(scr);
- return m_jump;
- }
-
- Jump branchTrue()
- {
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
- Jump m_jump = Jump(m_assembler.je());
- m_assembler.extraInstrForBranch(scratchReg3);
- return m_jump;
- }
-
- Jump branchFalse()
- {
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 6, sizeof(uint32_t));
- Jump m_jump = Jump(m_assembler.jne());
- m_assembler.extraInstrForBranch(scratchReg3);
- return m_jump;
- }
-
- Jump branch32(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
- {
- RegisterID scr = claimScratch();
- move(left.index, scr);
- lshift32(TrustedImm32(left.scale), scr);
- add32(left.base, scr);
- load32(scr, left.offset, scr);
- compare32(right.m_value, scr, cond);
- releaseScratch(scr);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- void sqrtDouble(FPRegisterID src, FPRegisterID dest)
- {
- if (dest != src)
- m_assembler.dmovRegReg(src, dest);
- m_assembler.dsqrt(dest);
- }
-
- void absDouble(FPRegisterID, FPRegisterID)
- {
- RELEASE_ASSERT_NOT_REACHED();
- }
-
- Jump branchTest8(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
- {
- RegisterID addressTempRegister = claimScratch();
- load8(address, addressTempRegister);
- Jump jmp = branchTest32(cond, addressTempRegister, mask);
- releaseScratch(addressTempRegister);
- return jmp;
- }
-
- Jump branchTest8(ResultCondition cond, AbsoluteAddress address, TrustedImm32 mask = TrustedImm32(-1))
- {
- RegisterID addressTempRegister = claimScratch();
- move(TrustedImmPtr(address.m_ptr), addressTempRegister);
- load8(Address(addressTempRegister), addressTempRegister);
- Jump jmp = branchTest32(cond, addressTempRegister, mask);
- releaseScratch(addressTempRegister);
- return jmp;
- }
-
- void signExtend32ToPtr(RegisterID src, RegisterID dest)
- {
- if (src != dest)
- move(src, dest);
- }
-
- Jump branch8(RelationalCondition cond, Address left, TrustedImm32 right)
- {
- RegisterID addressTempRegister = claimScratch();
- load8(left, addressTempRegister);
- Jump jmp = branch32(cond, addressTempRegister, right);
- releaseScratch(addressTempRegister);
- return jmp;
- }
-
- void compare8(RelationalCondition cond, Address left, TrustedImm32 right, RegisterID dest)
- {
- RegisterID addressTempRegister = claimScratch();
- load8(left, addressTempRegister);
- compare32(cond, addressTempRegister, right, dest);
- releaseScratch(addressTempRegister);
- }
-
- Jump branchTruncateDoubleToInt32(FPRegisterID src, RegisterID dest)
- {
- m_assembler.ftrcdrmfpul(src);
- m_assembler.stsfpulReg(dest);
- m_assembler.loadConstant(0x7fffffff, scratchReg3);
- m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 14, sizeof(uint32_t));
- m_assembler.branch(BT_OPCODE, 2);
- m_assembler.addlImm8r(1, scratchReg3);
- m_assembler.cmplRegReg(dest, scratchReg3, SH4Condition(Equal));
- return branchTrue();
- }
-
- // Stack manipulation operations
-
- void pop(RegisterID dest)
- {
- m_assembler.popReg(dest);
- }
-
- void push(RegisterID src)
- {
- m_assembler.pushReg(src);
- }
-
- void push(Address address)
- {
- if (!address.offset) {
- push(address.base);
- return;
- }
-
- if ((address.offset < 0) || (address.offset >= 64)) {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, SH4Registers::sp);
- m_assembler.addlImm8r(-4, SH4Registers::sp);
- releaseScratch(scr);
- return;
- }
-
- m_assembler.movlMemReg(address.offset >> 2, address.base, SH4Registers::sp);
- m_assembler.addlImm8r(-4, SH4Registers::sp);
- }
-
- void push(TrustedImm32 imm)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(imm.m_value, scr);
- push(scr);
- releaseScratch(scr);
- }
-
- // Register move operations
-
- void move(TrustedImm32 imm, RegisterID dest)
- {
- m_assembler.loadConstant(imm.m_value, dest);
- }
-
- DataLabelPtr moveWithPatch(TrustedImmPtr initialValue, RegisterID dest)
- {
- m_assembler.ensureSpace(m_assembler.maxInstructionSize, sizeof(uint32_t));
- DataLabelPtr dataLabel(this);
- m_assembler.loadConstantUnReusable(reinterpret_cast<uint32_t>(initialValue.m_value), dest);
- return dataLabel;
- }
-
- void move(RegisterID src, RegisterID dest)
- {
- if (src != dest)
- m_assembler.movlRegReg(src, dest);
- }
-
- void move(TrustedImmPtr imm, RegisterID dest)
- {
- m_assembler.loadConstant(imm.asIntptr(), dest);
- }
-
- void extuw(RegisterID src, RegisterID dst)
- {
- m_assembler.extuw(src, dst);
- }
-
- void compare32(RelationalCondition cond, RegisterID left, RegisterID right, RegisterID dest)
- {
- m_assembler.cmplRegReg(right, left, SH4Condition(cond));
- if (cond != NotEqual) {
- m_assembler.movt(dest);
- return;
- }
-
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 4);
- m_assembler.movImm8(0, dest);
- m_assembler.branch(BT_OPCODE, 0);
- m_assembler.movImm8(1, dest);
- }
-
- void compare32(RelationalCondition cond, RegisterID left, TrustedImm32 right, RegisterID dest)
- {
- if (left != dest) {
- move(right, dest);
- compare32(cond, left, dest, dest);
- return;
- }
-
- RegisterID scr = claimScratch();
- move(right, scr);
- compare32(cond, left, scr, dest);
- releaseScratch(scr);
- }
-
- void test8(ResultCondition cond, Address address, TrustedImm32 mask, RegisterID dest)
- {
- ASSERT((cond == Zero) || (cond == NonZero));
-
- load8(address, dest);
- if (mask.m_value == -1)
- compare32(0, dest, static_cast<RelationalCondition>(cond));
- else
- testlImm(mask.m_value, dest);
- if (cond != NonZero) {
- m_assembler.movt(dest);
- return;
- }
-
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 4);
- m_assembler.movImm8(0, dest);
- m_assembler.branch(BT_OPCODE, 0);
- m_assembler.movImm8(1, dest);
- }
-
- void loadPtrLinkReg(ImplicitAddress address)
- {
- RegisterID scr = claimScratch();
- load32(address, scr);
- m_assembler.ldspr(scr);
- releaseScratch(scr);
- }
-
- Jump branch32(RelationalCondition cond, RegisterID left, RegisterID right)
- {
- m_assembler.cmplRegReg(right, left, SH4Condition(cond));
- /* BT label => BF off
- nop LDR reg
- nop braf @reg
- nop nop
- */
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, RegisterID left, TrustedImm32 right)
- {
- if (((cond == Equal) || (cond == NotEqual)) && !right.m_value)
- m_assembler.testlRegReg(left, left);
- else
- compare32(right.m_value, left, cond);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, RegisterID left, Address right)
- {
- compare32(right.offset, right.base, left, cond);
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, Address left, RegisterID right)
- {
- compare32(right, left.offset, left.base, cond);
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, Address left, TrustedImm32 right)
- {
- compare32(right.m_value, left.offset, left.base, cond);
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, AbsoluteAddress left, RegisterID right)
- {
- RegisterID scr = claimScratch();
-
- move(TrustedImm32(reinterpret_cast<uint32_t>(left.m_ptr)), scr);
- m_assembler.cmplRegReg(right, scr, SH4Condition(cond));
- releaseScratch(scr);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch32(RelationalCondition cond, AbsoluteAddress left, TrustedImm32 right)
- {
- RegisterID addressTempRegister = claimScratch();
-
- m_assembler.loadConstant(reinterpret_cast<uint32_t>(left.m_ptr), addressTempRegister);
- m_assembler.movlMemReg(addressTempRegister, addressTempRegister);
- compare32(right.m_value, addressTempRegister, cond);
- releaseScratch(addressTempRegister);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branch8(RelationalCondition cond, BaseIndex left, TrustedImm32 right)
- {
- ASSERT(!(right.m_value & 0xFFFFFF00));
- RegisterID scr = claimScratch();
-
- move(left.index, scr);
- lshift32(TrustedImm32(left.scale), scr);
-
- if (left.offset)
- add32(TrustedImm32(left.offset), scr);
- add32(left.base, scr);
- load8(scr, scr);
- RegisterID scr1 = claimScratch();
- m_assembler.loadConstant(right.m_value, scr1);
- releaseScratch(scr);
- releaseScratch(scr1);
-
- return branch32(cond, scr, scr1);
- }
-
- Jump branchTest32(ResultCondition cond, RegisterID reg, RegisterID mask)
- {
- ASSERT((cond == Zero) || (cond == NonZero));
-
- m_assembler.testlRegReg(reg, mask);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchTest32(ResultCondition cond, RegisterID reg, TrustedImm32 mask = TrustedImm32(-1))
- {
- ASSERT((cond == Zero) || (cond == NonZero));
-
- if (mask.m_value == -1)
- m_assembler.testlRegReg(reg, reg);
- else
- testlImm(mask.m_value, reg);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchTest32(ResultCondition cond, Address address, TrustedImm32 mask = TrustedImm32(-1))
- {
- ASSERT((cond == Zero) || (cond == NonZero));
-
- if (mask.m_value == -1)
- compare32(0, address.offset, address.base, static_cast<RelationalCondition>(cond));
- else
- testImm(mask.m_value, address.offset, address.base);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchTest32(ResultCondition cond, BaseIndex address, TrustedImm32 mask = TrustedImm32(-1))
- {
- RegisterID scr = claimScratch();
-
- move(address.index, scr);
- lshift32(TrustedImm32(address.scale), scr);
- add32(address.base, scr);
- load32(scr, address.offset, scr);
-
- if (mask.m_value == -1)
- m_assembler.testlRegReg(scr, scr);
- else
- testlImm(mask.m_value, scr);
-
- releaseScratch(scr);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump jump()
- {
- return Jump(m_assembler.jmp());
- }
-
- void jump(RegisterID target)
- {
- m_assembler.jmpReg(target);
- }
-
- void jump(Address address)
- {
- RegisterID scr = claimScratch();
-
- if ((address.offset < 0) || (address.offset >= 64)) {
- m_assembler.loadConstant(address.offset, scr);
- m_assembler.addlRegReg(address.base, scr);
- m_assembler.movlMemReg(scr, scr);
- } else if (address.offset)
- m_assembler.movlMemReg(address.offset >> 2, address.base, scr);
- else
- m_assembler.movlMemReg(address.base, scr);
- m_assembler.jmpReg(scr);
-
- releaseScratch(scr);
- }
-
- // Arithmetic control flow operations
-
- Jump branchAdd32(ResultCondition cond, RegisterID src, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- if (cond == Overflow) {
- m_assembler.addvlRegReg(src, dest);
- return branchTrue();
- }
-
- if (cond == Signed) {
- m_assembler.addlRegReg(src, dest);
- // Check if dest is negative
- m_assembler.cmppz(dest);
- return branchFalse();
- }
-
- m_assembler.addlRegReg(src, dest);
- compare32(0, dest, Equal);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchAdd32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- move(imm, scratchReg3);
- return branchAdd32(cond, scratchReg3, dest);
- }
-
- Jump branchAdd32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- if (src != dest)
- move(src, dest);
-
- if (cond == Overflow) {
- move(imm, scratchReg3);
- m_assembler.addvlRegReg(scratchReg3, dest);
- return branchTrue();
- }
-
- add32(imm, dest);
-
- if (cond == Signed) {
- m_assembler.cmppz(dest);
- return branchFalse();
- }
-
- compare32(0, dest, Equal);
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchMul32(ResultCondition cond, RegisterID src, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- if (cond == Overflow) {
- RegisterID scr1 = claimScratch();
- RegisterID scr = claimScratch();
- m_assembler.dmullRegReg(src, dest);
- m_assembler.stsmacl(dest);
- m_assembler.movImm8(-31, scr);
- m_assembler.movlRegReg(dest, scr1);
- m_assembler.shaRegReg(scr1, scr);
- m_assembler.stsmach(scr);
- m_assembler.cmplRegReg(scr, scr1, SH4Condition(Equal));
- releaseScratch(scr1);
- releaseScratch(scr);
- return branchFalse();
- }
-
- m_assembler.imullRegReg(src, dest);
- m_assembler.stsmacl(dest);
- if (cond == Signed) {
- // Check if dest is negative
- m_assembler.cmppz(dest);
- return branchFalse();
- }
-
- compare32(0, dest, static_cast<RelationalCondition>(cond));
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchMul32(ResultCondition cond, TrustedImm32 imm, RegisterID src, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- move(imm, scratchReg3);
- if (src != dest)
- move(src, dest);
-
- return branchMul32(cond, scratchReg3, dest);
- }
-
- Jump branchSub32(ResultCondition cond, RegisterID src, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- if (cond == Overflow) {
- m_assembler.subvlRegReg(src, dest);
- return branchTrue();
- }
-
- if (cond == Signed) {
- // Check if dest is negative
- m_assembler.sublRegReg(src, dest);
- compare32(0, dest, LessThan);
- return branchTrue();
- }
-
- sub32(src, dest);
- compare32(0, dest, static_cast<RelationalCondition>(cond));
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchSub32(ResultCondition cond, TrustedImm32 imm, RegisterID dest)
- {
- ASSERT((cond == Overflow) || (cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- move(imm, scratchReg3);
- return branchSub32(cond, scratchReg3, dest);
- }
-
- Jump branchSub32(ResultCondition cond, RegisterID src, TrustedImm32 imm, RegisterID dest)
- {
- move(imm, scratchReg3);
- if (src != dest)
- move(src, dest);
- return branchSub32(cond, scratchReg3, dest);
- }
-
- Jump branchSub32(ResultCondition cond, RegisterID src1, RegisterID src2, RegisterID dest)
- {
- if (src1 != dest)
- move(src1, dest);
- return branchSub32(cond, src2, dest);
- }
-
- Jump branchOr32(ResultCondition cond, RegisterID src, RegisterID dest)
- {
- ASSERT((cond == Signed) || (cond == Zero) || (cond == NonZero));
-
- if (cond == Signed) {
- or32(src, dest);
- compare32(0, dest, static_cast<RelationalCondition>(LessThan));
- return branchTrue();
- }
-
- or32(src, dest);
- compare32(0, dest, static_cast<RelationalCondition>(cond));
-
- if (cond == NonZero) // NotEqual
- return branchFalse();
- return branchTrue();
- }
-
- void branchConvertDoubleToInt32(FPRegisterID src, RegisterID dest, JumpList& failureCases, FPRegisterID fpTemp)
- {
- m_assembler.ftrcdrmfpul(src);
- m_assembler.stsfpulReg(dest);
- convertInt32ToDouble(dest, fscratch);
- failureCases.append(branchDouble(DoubleNotEqualOrUnordered, fscratch, src));
-
- if (dest == SH4Registers::r0)
- m_assembler.cmpEqImmR0(0, dest);
- else {
- m_assembler.movImm8(0, scratchReg3);
- m_assembler.cmplRegReg(scratchReg3, dest, SH4Condition(Equal));
- }
- failureCases.append(branchTrue());
- }
-
- void neg32(RegisterID dst)
- {
- m_assembler.neg(dst, dst);
- }
-
- void urshift32(RegisterID shiftamount, RegisterID dest)
- {
- if (shiftamount == SH4Registers::r0)
- m_assembler.andlImm8r(0x1f, shiftamount);
- else {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(0x1f, scr);
- m_assembler.andlRegReg(scr, shiftamount);
- releaseScratch(scr);
- }
- m_assembler.neg(shiftamount, shiftamount);
- m_assembler.shllRegReg(dest, shiftamount);
- }
-
- void urshift32(TrustedImm32 imm, RegisterID dest)
- {
- RegisterID scr = claimScratch();
- m_assembler.loadConstant(-(imm.m_value & 0x1f), scr);
- m_assembler.shaRegReg(dest, scr);
- releaseScratch(scr);
- }
-
- void urshift32(RegisterID src, TrustedImm32 shiftamount, RegisterID dest)
- {
- if (src != dest)
- move(src, dest);
-
- urshift32(shiftamount, dest);
- }
-
- Call call()
- {
- return Call(m_assembler.call(), Call::Linkable);
- }
-
- Call nearCall()
- {
- return Call(m_assembler.call(), Call::LinkableNear);
- }
-
- Call call(RegisterID target)
- {
- return Call(m_assembler.call(target), Call::None);
- }
-
- void call(Address address, RegisterID target)
- {
- load32(address.base, address.offset, target);
- m_assembler.ensureSpace(m_assembler.maxInstructionSize + 2);
- m_assembler.branch(JSR_OPCODE, target);
- m_assembler.nop();
- }
-
- void breakpoint()
- {
- m_assembler.bkpt();
- m_assembler.nop();
- }
-
- Jump branchPtrWithPatch(RelationalCondition cond, RegisterID left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
- {
- RegisterID dataTempRegister = claimScratch();
-
- dataLabel = moveWithPatch(initialRightValue, dataTempRegister);
- m_assembler.cmplRegReg(dataTempRegister, left, SH4Condition(cond));
- releaseScratch(dataTempRegister);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- Jump branchPtrWithPatch(RelationalCondition cond, Address left, DataLabelPtr& dataLabel, TrustedImmPtr initialRightValue = TrustedImmPtr(0))
- {
- RegisterID scr = claimScratch();
-
- m_assembler.loadConstant(left.offset, scr);
- m_assembler.addlRegReg(left.base, scr);
- m_assembler.movlMemReg(scr, scr);
- RegisterID scr1 = claimScratch();
- dataLabel = moveWithPatch(initialRightValue, scr1);
- m_assembler.cmplRegReg(scr1, scr, SH4Condition(cond));
- releaseScratch(scr);
- releaseScratch(scr1);
-
- if (cond == NotEqual)
- return branchFalse();
- return branchTrue();
- }
-
- void ret()
- {
- m_assembler.ret();
- m_assembler.nop();
- }
-
- DataLabelPtr storePtrWithPatch(TrustedImmPtr initialValue, ImplicitAddress address)
- {
- RegisterID scr = claimScratch();
- DataLabelPtr label = moveWithPatch(initialValue, scr);
- store32(scr, address);
- releaseScratch(scr);
- return label;
- }
-
- DataLabelPtr storePtrWithPatch(ImplicitAddress address) { return storePtrWithPatch(TrustedImmPtr(0), address); }
-
- int sizeOfConstantPool()
- {
- return m_assembler.sizeOfConstantPool();
- }
-
- Call tailRecursiveCall()
- {
- RegisterID scr = claimScratch();
-
- m_assembler.loadConstantUnReusable(0x0, scr, true);
- Jump m_jump = Jump(m_assembler.jmp(scr));
- releaseScratch(scr);
-
- return Call::fromTailJump(m_jump);
- }
-
- Call makeTailRecursiveCall(Jump oldJump)
- {
- oldJump.link(this);
- return tailRecursiveCall();
- }
-
- void nop()
- {
- m_assembler.nop();
- }
-
- static FunctionPtr readCallTarget(CodeLocationCall call)
- {
- return FunctionPtr(reinterpret_cast<void(*)()>(SH4Assembler::readCallTarget(call.dataLocation())));
- }
-
- static void replaceWithJump(CodeLocationLabel instructionStart, CodeLocationLabel destination)
- {
- RELEASE_ASSERT_NOT_REACHED();
- }
-
- static ptrdiff_t maxJumpReplacementSize()
- {
- RELEASE_ASSERT_NOT_REACHED();
- return 0;
- }
-
- static bool canJumpReplacePatchableBranchPtrWithPatch() { return false; }
-
- static CodeLocationLabel startOfBranchPtrWithPatchOnRegister(CodeLocationDataLabelPtr label)
- {
- return label.labelAtOffset(0);
- }
-
- static void revertJumpReplacementToBranchPtrWithPatch(CodeLocationLabel instructionStart, RegisterID, void* initialValue)
- {
- SH4Assembler::revertJump(instructionStart.dataLocation(), reinterpret_cast<uintptr_t>(initialValue) & 0xffff);
- }
-
- static CodeLocationLabel startOfPatchableBranchPtrWithPatchOnAddress(CodeLocationDataLabelPtr)
- {
- UNREACHABLE_FOR_PLATFORM();
- return CodeLocationLabel();
- }
-
- static void revertJumpReplacementToPatchableBranchPtrWithPatch(CodeLocationLabel instructionStart, Address, void* initialValue)
- {
- UNREACHABLE_FOR_PLATFORM();
- }
-
-protected:
- SH4Assembler::Condition SH4Condition(RelationalCondition cond)
- {
- return static_cast<SH4Assembler::Condition>(cond);
- }
-
- SH4Assembler::Condition SH4Condition(ResultCondition cond)
- {
- return static_cast<SH4Assembler::Condition>(cond);
- }
-private:
- template <typename, template <typename> class> friend class LinkBufferBase;
- friend class RepatchBuffer;
-
- static void linkCall(void*, Call, FunctionPtr);
- static void repatchCall(CodeLocationCall, CodeLocationLabel);
- static void repatchCall(CodeLocationCall, FunctionPtr);
-};
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER)
-
-#endif // MacroAssemblerSH4_h
diff --git a/src/3rdparty/masm/assembler/SH4Assembler.h b/src/3rdparty/masm/assembler/SH4Assembler.h
deleted file mode 100644
index b7a166ea99..0000000000
--- a/src/3rdparty/masm/assembler/SH4Assembler.h
+++ /dev/null
@@ -1,2152 +0,0 @@
-/*
- * Copyright (C) 2009-2011 STMicroelectronics. All rights reserved.
- * Copyright (C) 2008 Apple Inc. All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- * 1. Redistributions of source code must retain the above copyright
- * notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- * notice, this list of conditions and the following disclaimer in the
- * documentation and/or other materials provided with the distribution.
- *
- * THIS SOFTWARE IS PROVIDED BY APPLE INC. ``AS IS'' AND ANY
- * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
- * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL APPLE INC. OR
- * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
- * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
- * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
- * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY
- * OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef SH4Assembler_h
-#define SH4Assembler_h
-
-#if ENABLE(ASSEMBLER) && CPU(SH4)
-
-#include "AssemblerBuffer.h"
-#include "AssemblerBufferWithConstantPool.h"
-#include "JITCompilationEffort.h"
-#include <stdarg.h>
-#include <stdint.h>
-#include <stdio.h>
-#include <wtf/Assertions.h>
-#include <wtf/DataLog.h>
-#include <wtf/Vector.h>
-
-#ifndef NDEBUG
-#define SH4_ASSEMBLER_TRACING
-#endif
-
-namespace JSC {
-typedef uint16_t SH4Word;
-
-enum {
- INVALID_OPCODE = 0xffff,
- ADD_OPCODE = 0x300c,
- ADDIMM_OPCODE = 0x7000,
- ADDC_OPCODE = 0x300e,
- ADDV_OPCODE = 0x300f,
- AND_OPCODE = 0x2009,
- ANDIMM_OPCODE = 0xc900,
- DIV0_OPCODE = 0x2007,
- DIV1_OPCODE = 0x3004,
- BF_OPCODE = 0x8b00,
- BFS_OPCODE = 0x8f00,
- BRA_OPCODE = 0xa000,
- BRAF_OPCODE = 0x0023,
- NOP_OPCODE = 0x0009,
- BSR_OPCODE = 0xb000,
- RTS_OPCODE = 0x000b,
- BT_OPCODE = 0x8900,
- BTS_OPCODE = 0x8d00,
- BSRF_OPCODE = 0x0003,
- BRK_OPCODE = 0x003b,
- FTRC_OPCODE = 0xf03d,
- CMPEQ_OPCODE = 0x3000,
- CMPEQIMM_OPCODE = 0x8800,
- CMPGE_OPCODE = 0x3003,
- CMPGT_OPCODE = 0x3007,
- CMPHI_OPCODE = 0x3006,
- CMPHS_OPCODE = 0x3002,
- CMPPL_OPCODE = 0x4015,
- CMPPZ_OPCODE = 0x4011,
- CMPSTR_OPCODE = 0x200c,
- DT_OPCODE = 0x4010,
- FCMPEQ_OPCODE = 0xf004,
- FCMPGT_OPCODE = 0xf005,
- FMOV_OPCODE = 0xf00c,
- FADD_OPCODE = 0xf000,
- FMUL_OPCODE = 0xf002,
- FSUB_OPCODE = 0xf001,
- FDIV_OPCODE = 0xf003,
- FNEG_OPCODE = 0xf04d,
- JMP_OPCODE = 0x402b,
- JSR_OPCODE = 0x400b,
- LDSPR_OPCODE = 0x402a,
- LDSLPR_OPCODE = 0x4026,
- MOV_OPCODE = 0x6003,
- MOVIMM_OPCODE = 0xe000,
- MOVB_WRITE_RN_OPCODE = 0x2000,
- MOVB_WRITE_RNDEC_OPCODE = 0x2004,
- MOVB_WRITE_R0RN_OPCODE = 0x0004,
- MOVB_WRITE_OFFGBR_OPCODE = 0xc000,
- MOVB_WRITE_OFFRN_OPCODE = 0x8000,
- MOVB_READ_RM_OPCODE = 0x6000,
- MOVB_READ_RMINC_OPCODE = 0x6004,
- MOVB_READ_R0RM_OPCODE = 0x000c,
- MOVB_READ_OFFGBR_OPCODE = 0xc400,
- MOVB_READ_OFFRM_OPCODE = 0x8400,
- MOVL_WRITE_RN_OPCODE = 0x2002,
- MOVL_WRITE_RNDEC_OPCODE = 0x2006,
- MOVL_WRITE_R0RN_OPCODE = 0x0006,
- MOVL_WRITE_OFFGBR_OPCODE = 0xc200,
- MOVL_WRITE_OFFRN_OPCODE = 0x1000,
- MOVL_READ_RM_OPCODE = 0x6002,
- MOVL_READ_RMINC_OPCODE = 0x6006,
- MOVL_READ_R0RM_OPCODE = 0x000e,
- MOVL_READ_OFFGBR_OPCODE = 0xc600,
- MOVL_READ_OFFPC_OPCODE = 0xd000,
- MOVL_READ_OFFRM_OPCODE = 0x5000,
- MOVW_WRITE_RN_OPCODE = 0x2001,
- MOVW_READ_RM_OPCODE = 0x6001,
- MOVW_READ_R0RM_OPCODE = 0x000d,
- MOVW_READ_OFFRM_OPCODE = 0x8500,
- MOVW_READ_OFFPC_OPCODE = 0x9000,
- MOVA_READ_OFFPC_OPCODE = 0xc700,
- MOVT_OPCODE = 0x0029,
- MULL_OPCODE = 0x0007,
- DMULL_L_OPCODE = 0x3005,
- STSMACL_OPCODE = 0x001a,
- STSMACH_OPCODE = 0x000a,
- DMULSL_OPCODE = 0x300d,
- NEG_OPCODE = 0x600b,
- NEGC_OPCODE = 0x600a,
- NOT_OPCODE = 0x6007,
- OR_OPCODE = 0x200b,
- ORIMM_OPCODE = 0xcb00,
- ORBIMM_OPCODE = 0xcf00,
- SETS_OPCODE = 0x0058,
- SETT_OPCODE = 0x0018,
- SHAD_OPCODE = 0x400c,
- SHAL_OPCODE = 0x4020,
- SHAR_OPCODE = 0x4021,
- SHLD_OPCODE = 0x400d,
- SHLL_OPCODE = 0x4000,
- SHLL2_OPCODE = 0x4008,
- SHLL8_OPCODE = 0x4018,
- SHLL16_OPCODE = 0x4028,
- SHLR_OPCODE = 0x4001,
- SHLR2_OPCODE = 0x4009,
- SHLR8_OPCODE = 0x4019,
- SHLR16_OPCODE = 0x4029,
- STSPR_OPCODE = 0x002a,
- STSLPR_OPCODE = 0x4022,
- FLOAT_OPCODE = 0xf02d,
- SUB_OPCODE = 0x3008,
- SUBC_OPCODE = 0x300a,
- SUBV_OPCODE = 0x300b,
- TST_OPCODE = 0x2008,
- TSTIMM_OPCODE = 0xc800,
- TSTB_OPCODE = 0xcc00,
- EXTUB_OPCODE = 0x600c,
- EXTUW_OPCODE = 0x600d,
- XOR_OPCODE = 0x200a,
- XORIMM_OPCODE = 0xca00,
- XORB_OPCODE = 0xce00,
- FMOVS_READ_RM_INC_OPCODE = 0xf009,
- FMOVS_READ_RM_OPCODE = 0xf008,
- FMOVS_READ_R0RM_OPCODE = 0xf006,
- FMOVS_WRITE_RN_OPCODE = 0xf00a,
- FMOVS_WRITE_RN_DEC_OPCODE = 0xf00b,
- FMOVS_WRITE_R0RN_OPCODE = 0xf007,
- FCNVDS_DRM_FPUL_OPCODE = 0xf0bd,
- FCNVSD_FPUL_DRN_OPCODE = 0xf0ad,
- LDS_RM_FPUL_OPCODE = 0x405a,
- FLDS_FRM_FPUL_OPCODE = 0xf01d,
- STS_FPUL_RN_OPCODE = 0x005a,
- FSTS_FPUL_FRN_OPCODE = 0xF00d,
- LDSFPSCR_OPCODE = 0x406a,
- STSFPSCR_OPCODE = 0x006a,
- LDSRMFPUL_OPCODE = 0x405a,
- FSTSFPULFRN_OPCODE = 0xf00d,
- FSQRT_OPCODE = 0xf06d,
- FSCHG_OPCODE = 0xf3fd,
- CLRT_OPCODE = 8,
-};
-
-namespace SH4Registers {
-typedef enum {
- r0,
- r1,
- r2,
- r3,
- r4,
- r5,
- r6,
- r7,
- r8,
- r9,
- r10,
- r11,
- r12,
- r13,
- r14, fp = r14,
- r15, sp = r15,
- pc,
- pr,
-} RegisterID;
-
-typedef enum {
- fr0, dr0 = fr0,
- fr1,
- fr2, dr2 = fr2,
- fr3,
- fr4, dr4 = fr4,
- fr5,
- fr6, dr6 = fr6,
- fr7,
- fr8, dr8 = fr8,
- fr9,
- fr10, dr10 = fr10,
- fr11,
- fr12, dr12 = fr12,
- fr13,
- fr14, dr14 = fr14,
- fr15,
-} FPRegisterID;
-}
-
-inline uint16_t getOpcodeGroup1(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4));
-}
-
-inline uint16_t getOpcodeGroup2(uint16_t opc, int rm)
-{
- return (opc | ((rm & 0xf) << 8));
-}
-
-inline uint16_t getOpcodeGroup3(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0xf) << 8) | (rn & 0xff));
-}
-
-inline uint16_t getOpcodeGroup4(uint16_t opc, int rm, int rn, int offset)
-{
- return (opc | ((rm & 0xf) << 8) | ((rn & 0xf) << 4) | (offset & 0xf));
-}
-
-inline uint16_t getOpcodeGroup5(uint16_t opc, int rm)
-{
- return (opc | (rm & 0xff));
-}
-
-inline uint16_t getOpcodeGroup6(uint16_t opc, int rm)
-{
- return (opc | (rm & 0xfff));
-}
-
-inline uint16_t getOpcodeGroup7(uint16_t opc, int rm)
-{
- return (opc | ((rm & 0x7) << 9));
-}
-
-inline uint16_t getOpcodeGroup8(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0x7) << 9) | ((rn & 0x7) << 5));
-}
-
-inline uint16_t getOpcodeGroup9(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0xf) << 8) | ((rn & 0x7) << 5));
-}
-
-inline uint16_t getOpcodeGroup10(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0x7) << 9) | ((rn & 0xf) << 4));
-}
-
-inline uint16_t getOpcodeGroup11(uint16_t opc, int rm, int rn)
-{
- return (opc | ((rm & 0xf) << 4) | (rn & 0xf));
-}
-
-inline uint16_t getRn(uint16_t x)
-{
- return ((x & 0xf00) >> 8);
-}
-
-inline uint16_t getRm(uint16_t x)
-{
- return ((x & 0xf0) >> 4);
-}
-
-inline uint16_t getDisp(uint16_t x)
-{
- return (x & 0xf);
-}
-
-inline uint16_t getImm8(uint16_t x)
-{
- return (x & 0xff);
-}
-
-inline uint16_t getImm12(uint16_t x)
-{
- return (x & 0xfff);
-}
-
-inline uint16_t getDRn(uint16_t x)
-{
- return ((x & 0xe00) >> 9);
-}
-
-inline uint16_t getDRm(uint16_t x)
-{
- return ((x & 0xe0) >> 5);
-}
-
-class SH4Assembler {
-public:
- typedef SH4Registers::RegisterID RegisterID;
- typedef SH4Registers::FPRegisterID FPRegisterID;
- typedef AssemblerBufferWithConstantPool<512, 4, 2, SH4Assembler> SH4Buffer;
- static const RegisterID scratchReg1 = SH4Registers::r3;
- static const RegisterID scratchReg2 = SH4Registers::r11;
- static const uint32_t maxInstructionSize = 16;
-
- enum {
- padForAlign8 = 0x00,
- padForAlign16 = 0x0009,
- padForAlign32 = 0x00090009,
- };
-
- enum JumpType {
- JumpFar,
- JumpNear
- };
-
- SH4Assembler()
- {
- m_claimscratchReg = 0x0;
- }
-
- // SH4 condition codes
- typedef enum {
- EQ = 0x0, // Equal
- NE = 0x1, // Not Equal
- HS = 0x2, // Unsigend Greater Than equal
- HI = 0x3, // Unsigend Greater Than
- LS = 0x4, // Unsigend Lower or Same
- LI = 0x5, // Unsigend Lower
- GE = 0x6, // Greater or Equal
- LT = 0x7, // Less Than
- GT = 0x8, // Greater Than
- LE = 0x9, // Less or Equal
- OF = 0xa, // OverFlow
- SI = 0xb, // Signed
- EQU= 0xc, // Equal or unordered(NaN)
- NEU= 0xd,
- GTU= 0xe,
- GEU= 0xf,
- LTU= 0x10,
- LEU= 0x11,
- } Condition;
-
- // Opaque label types
-public:
- bool isImmediate(int constant)
- {
- return ((constant <= 127) && (constant >= -128));
- }
-
- RegisterID claimScratch()
- {
- ASSERT((m_claimscratchReg != 0x3));
-
- if (!(m_claimscratchReg & 0x1)) {
- m_claimscratchReg = (m_claimscratchReg | 0x1);
- return scratchReg1;
- }
-
- m_claimscratchReg = (m_claimscratchReg | 0x2);
- return scratchReg2;
- }
-
- void releaseScratch(RegisterID scratchR)
- {
- if (scratchR == scratchReg1)
- m_claimscratchReg = (m_claimscratchReg & 0x2);
- else
- m_claimscratchReg = (m_claimscratchReg & 0x1);
- }
-
- // Stack operations
-
- void pushReg(RegisterID reg)
- {
- if (reg == SH4Registers::pr) {
- oneShortOp(getOpcodeGroup2(STSLPR_OPCODE, SH4Registers::sp));
- return;
- }
-
- oneShortOp(getOpcodeGroup1(MOVL_WRITE_RNDEC_OPCODE, SH4Registers::sp, reg));
- }
-
- void popReg(RegisterID reg)
- {
- if (reg == SH4Registers::pr) {
- oneShortOp(getOpcodeGroup2(LDSLPR_OPCODE, SH4Registers::sp));
- return;
- }
-
- oneShortOp(getOpcodeGroup1(MOVL_READ_RMINC_OPCODE, reg, SH4Registers::sp));
- }
-
- void movt(RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup2(MOVT_OPCODE, dst);
- oneShortOp(opc);
- }
-
- // Arithmetic operations
-
- void addlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(ADD_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void addclRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(ADDC_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void addvlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(ADDV_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void addlImm8r(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 127) && (imm8 >= -128));
-
- uint16_t opc = getOpcodeGroup3(ADDIMM_OPCODE, dst, imm8);
- oneShortOp(opc);
- }
-
- void andlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(AND_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void andlImm8r(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 255) && (imm8 >= 0));
- ASSERT(dst == SH4Registers::r0);
-
- uint16_t opc = getOpcodeGroup5(ANDIMM_OPCODE, imm8);
- oneShortOp(opc);
- }
-
- void div1lRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(DIV1_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void div0lRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(DIV0_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void notlReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(NOT_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void orlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(OR_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void orlImm8r(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 255) && (imm8 >= 0));
- ASSERT(dst == SH4Registers::r0);
-
- uint16_t opc = getOpcodeGroup5(ORIMM_OPCODE, imm8);
- oneShortOp(opc);
- }
-
- void sublRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(SUB_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void subvlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(SUBV_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void xorlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(XOR_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void xorlImm8r(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 255) && (imm8 >= 0));
- ASSERT(dst == SH4Registers::r0);
-
- uint16_t opc = getOpcodeGroup5(XORIMM_OPCODE, imm8);
- oneShortOp(opc);
- }
-
- void shllImm8r(int imm, RegisterID dst)
- {
- switch (imm) {
- case 1:
- oneShortOp(getOpcodeGroup2(SHLL_OPCODE, dst));
- break;
- case 2:
- oneShortOp(getOpcodeGroup2(SHLL2_OPCODE, dst));
- break;
- case 8:
- oneShortOp(getOpcodeGroup2(SHLL8_OPCODE, dst));
- break;
- case 16:
- oneShortOp(getOpcodeGroup2(SHLL16_OPCODE, dst));
- break;
- default:
- RELEASE_ASSERT_NOT_REACHED();
- }
- }
-
- void neg(RegisterID dst, RegisterID src)
- {
- uint16_t opc = getOpcodeGroup1(NEG_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void shllRegReg(RegisterID dst, RegisterID rShift)
- {
- uint16_t opc = getOpcodeGroup1(SHLD_OPCODE, dst, rShift);
- oneShortOp(opc);
- }
-
- void shlrRegReg(RegisterID dst, RegisterID rShift)
- {
- neg(rShift, rShift);
- shllRegReg(dst, rShift);
- }
-
- void sharRegReg(RegisterID dst, RegisterID rShift)
- {
- neg(rShift, rShift);
- shaRegReg(dst, rShift);
- }
-
- void shaRegReg(RegisterID dst, RegisterID rShift)
- {
- uint16_t opc = getOpcodeGroup1(SHAD_OPCODE, dst, rShift);
- oneShortOp(opc);
- }
-
- void shlrImm8r(int imm, RegisterID dst)
- {
- switch (imm) {
- case 1:
- oneShortOp(getOpcodeGroup2(SHLR_OPCODE, dst));
- break;
- case 2:
- oneShortOp(getOpcodeGroup2(SHLR2_OPCODE, dst));
- break;
- case 8:
- oneShortOp(getOpcodeGroup2(SHLR8_OPCODE, dst));
- break;
- case 16:
- oneShortOp(getOpcodeGroup2(SHLR16_OPCODE, dst));
- break;
- default:
- RELEASE_ASSERT_NOT_REACHED();
- }
- }
-
- void imullRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MULL_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void dmullRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(DMULL_L_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void dmulslRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(DMULSL_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void stsmacl(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(STSMACL_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void stsmach(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(STSMACH_OPCODE, reg);
- oneShortOp(opc);
- }
-
- // Comparisons
-
- void cmplRegReg(RegisterID left, RegisterID right, Condition cond)
- {
- switch (cond) {
- case NE:
- oneShortOp(getOpcodeGroup1(CMPEQ_OPCODE, right, left));
- break;
- case GT:
- oneShortOp(getOpcodeGroup1(CMPGT_OPCODE, right, left));
- break;
- case EQ:
- oneShortOp(getOpcodeGroup1(CMPEQ_OPCODE, right, left));
- break;
- case GE:
- oneShortOp(getOpcodeGroup1(CMPGE_OPCODE, right, left));
- break;
- case HS:
- oneShortOp(getOpcodeGroup1(CMPHS_OPCODE, right, left));
- break;
- case HI:
- oneShortOp(getOpcodeGroup1(CMPHI_OPCODE, right, left));
- break;
- case LI:
- oneShortOp(getOpcodeGroup1(CMPHI_OPCODE, left, right));
- break;
- case LS:
- oneShortOp(getOpcodeGroup1(CMPHS_OPCODE, left, right));
- break;
- case LE:
- oneShortOp(getOpcodeGroup1(CMPGE_OPCODE, left, right));
- break;
- case LT:
- oneShortOp(getOpcodeGroup1(CMPGT_OPCODE, left, right));
- break;
- default:
- RELEASE_ASSERT_NOT_REACHED();
- }
- }
-
- void cmppl(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(CMPPL_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void cmppz(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(CMPPZ_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void cmpEqImmR0(int imm, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup5(CMPEQIMM_OPCODE, imm);
- oneShortOp(opc);
- }
-
- void testlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(TST_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void testlImm8r(int imm, RegisterID dst)
- {
- ASSERT((dst == SH4Registers::r0) && (imm <= 255) && (imm >= 0));
-
- uint16_t opc = getOpcodeGroup5(TSTIMM_OPCODE, imm);
- oneShortOp(opc);
- }
-
- void nop()
- {
- oneShortOp(NOP_OPCODE, false);
- }
-
- void sett()
- {
- oneShortOp(SETT_OPCODE);
- }
-
- void clrt()
- {
- oneShortOp(CLRT_OPCODE);
- }
-
- void fschg()
- {
- oneShortOp(FSCHG_OPCODE);
- }
-
- void bkpt()
- {
- oneShortOp(BRK_OPCODE, false);
- }
-
- void branch(uint16_t opc, int label)
- {
- switch (opc) {
- case BT_OPCODE:
- ASSERT((label <= 127) && (label >= -128));
- oneShortOp(getOpcodeGroup5(BT_OPCODE, label));
- break;
- case BRA_OPCODE:
- ASSERT((label <= 2047) && (label >= -2048));
- oneShortOp(getOpcodeGroup6(BRA_OPCODE, label));
- break;
- case BF_OPCODE:
- ASSERT((label <= 127) && (label >= -128));
- oneShortOp(getOpcodeGroup5(BF_OPCODE, label));
- break;
- default:
- RELEASE_ASSERT_NOT_REACHED();
- }
- }
-
- void branch(uint16_t opc, RegisterID reg)
- {
- switch (opc) {
- case BRAF_OPCODE:
- oneShortOp(getOpcodeGroup2(BRAF_OPCODE, reg));
- break;
- case JMP_OPCODE:
- oneShortOp(getOpcodeGroup2(JMP_OPCODE, reg));
- break;
- case JSR_OPCODE:
- oneShortOp(getOpcodeGroup2(JSR_OPCODE, reg));
- break;
- case BSRF_OPCODE:
- oneShortOp(getOpcodeGroup2(BSRF_OPCODE, reg));
- break;
- default:
- RELEASE_ASSERT_NOT_REACHED();
- }
- }
-
- void ldspr(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(LDSPR_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void stspr(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(STSPR_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void extub(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(EXTUB_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void extuw(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(EXTUW_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- // float operations
-
- void ldsrmfpul(RegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(LDS_RM_FPUL_OPCODE, src);
- oneShortOp(opc);
- }
-
- void fneg(FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup2(FNEG_OPCODE, dst);
- oneShortOp(opc, true, false);
- }
-
- void fsqrt(FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup2(FSQRT_OPCODE, dst);
- oneShortOp(opc, true, false);
- }
-
- void stsfpulReg(RegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(STS_FPUL_RN_OPCODE, src);
- oneShortOp(opc);
- }
-
- void floatfpulfrn(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(FLOAT_OPCODE, src);
- oneShortOp(opc, true, false);
- }
-
- void fmull(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMUL_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsReadrm(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsWriterm(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsWriter0r(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_R0RN_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsReadr0r(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_READ_R0RM_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsReadrminc(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_READ_RM_INC_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void fmovsWriterndec(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(FMOVS_WRITE_RN_DEC_OPCODE, dst, src);
- oneShortOp(opc, true, false);
- }
-
- void ftrcRegfpul(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(FTRC_OPCODE, src);
- oneShortOp(opc, true, false);
- }
-
- void fldsfpul(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(FLDS_FRM_FPUL_OPCODE, src);
- oneShortOp(opc);
- }
-
- void fstsfpul(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup2(FSTS_FPUL_FRN_OPCODE, src);
- oneShortOp(opc);
- }
-
- void ldsfpscr(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(LDSFPSCR_OPCODE, reg);
- oneShortOp(opc);
- }
-
- void stsfpscr(RegisterID reg)
- {
- uint16_t opc = getOpcodeGroup2(STSFPSCR_OPCODE, reg);
- oneShortOp(opc);
- }
-
- // double operations
-
- void dcnvds(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup7(FCNVDS_DRM_FPUL_OPCODE, src >> 1);
- oneShortOp(opc);
- }
-
- void dcnvsd(FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup7(FCNVSD_FPUL_DRN_OPCODE, dst >> 1);
- oneShortOp(opc);
- }
-
- void dcmppeq(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FCMPEQ_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void dcmppgt(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FCMPGT_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void dmulRegReg(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FMUL_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void dsubRegReg(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FSUB_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void daddRegReg(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FADD_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void dmovRegReg(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FMOV_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void ddivRegReg(FPRegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup8(FDIV_OPCODE, dst >> 1, src >> 1);
- oneShortOp(opc);
- }
-
- void dsqrt(FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup7(FSQRT_OPCODE, dst >> 1);
- oneShortOp(opc);
- }
-
- void dneg(FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup7(FNEG_OPCODE, dst >> 1);
- oneShortOp(opc);
- }
-
- void fmovReadrm(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_OPCODE, dst >> 1, src);
- oneShortOp(opc);
- }
-
- void fmovWriterm(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_OPCODE, dst, src >> 1);
- oneShortOp(opc);
- }
-
- void fmovWriter0r(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_R0RN_OPCODE, dst, src >> 1);
- oneShortOp(opc);
- }
-
- void fmovReadr0r(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup10(FMOVS_READ_R0RM_OPCODE, dst >> 1, src);
- oneShortOp(opc);
- }
-
- void fmovReadrminc(RegisterID src, FPRegisterID dst)
- {
- uint16_t opc = getOpcodeGroup10(FMOVS_READ_RM_INC_OPCODE, dst >> 1, src);
- oneShortOp(opc);
- }
-
- void fmovWriterndec(FPRegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup9(FMOVS_WRITE_RN_DEC_OPCODE, dst, src >> 1);
- oneShortOp(opc);
- }
-
- void floatfpulDreg(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup7(FLOAT_OPCODE, src >> 1);
- oneShortOp(opc);
- }
-
- void ftrcdrmfpul(FPRegisterID src)
- {
- uint16_t opc = getOpcodeGroup7(FTRC_OPCODE, src >> 1);
- oneShortOp(opc);
- }
-
- // Various move ops
-
- void movImm8(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 127) && (imm8 >= -128));
-
- uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8);
- oneShortOp(opc);
- }
-
- void movlRegReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOV_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movwRegMem(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVW_WRITE_RN_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movwMemReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVW_READ_RM_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movwPCReg(int offset, RegisterID base, RegisterID dst)
- {
- ASSERT(base == SH4Registers::pc);
- ASSERT((offset <= 255) && (offset >= 0));
-
- uint16_t opc = getOpcodeGroup3(MOVW_READ_OFFPC_OPCODE, dst, offset);
- oneShortOp(opc);
- }
-
- void movwMemReg(int offset, RegisterID base, RegisterID dst)
- {
- ASSERT(dst == SH4Registers::r0);
-
- uint16_t opc = getOpcodeGroup11(MOVW_READ_OFFRM_OPCODE, base, offset);
- oneShortOp(opc);
- }
-
- void movwR0mr(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVW_READ_R0RM_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movlRegMem(RegisterID src, int offset, RegisterID base)
- {
- ASSERT((offset <= 15) && (offset >= 0));
-
- if (!offset) {
- oneShortOp(getOpcodeGroup1(MOVL_WRITE_RN_OPCODE, base, src));
- return;
- }
-
- oneShortOp(getOpcodeGroup4(MOVL_WRITE_OFFRN_OPCODE, base, src, offset));
- }
-
- void movlRegMem(RegisterID src, RegisterID base)
- {
- uint16_t opc = getOpcodeGroup1(MOVL_WRITE_RN_OPCODE, base, src);
- oneShortOp(opc);
- }
-
- void movlMemReg(int offset, RegisterID base, RegisterID dst)
- {
- if (base == SH4Registers::pc) {
- ASSERT((offset <= 255) && (offset >= 0));
- oneShortOp(getOpcodeGroup3(MOVL_READ_OFFPC_OPCODE, dst, offset));
- return;
- }
-
- ASSERT((offset <= 15) && (offset >= 0));
- if (!offset) {
- oneShortOp(getOpcodeGroup1(MOVL_READ_RM_OPCODE, dst, base));
- return;
- }
-
- oneShortOp(getOpcodeGroup4(MOVL_READ_OFFRM_OPCODE, dst, base, offset));
- }
-
- void movlMemRegCompact(int offset, RegisterID base, RegisterID dst)
- {
- oneShortOp(getOpcodeGroup4(MOVL_READ_OFFRM_OPCODE, dst, base, offset));
- }
-
- void movbRegMem(RegisterID src, RegisterID base)
- {
- uint16_t opc = getOpcodeGroup1(MOVB_WRITE_RN_OPCODE, base, src);
- oneShortOp(opc);
- }
-
- void movbMemReg(int offset, RegisterID base, RegisterID dst)
- {
- ASSERT(dst == SH4Registers::r0);
-
- uint16_t opc = getOpcodeGroup11(MOVB_READ_OFFRM_OPCODE, base, offset);
- oneShortOp(opc);
- }
-
- void movbR0mr(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVB_READ_R0RM_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movbMemReg(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVB_READ_RM_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movlMemReg(RegisterID base, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVL_READ_RM_OPCODE, dst, base);
- oneShortOp(opc);
- }
-
- void movlMemRegIn(RegisterID base, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVL_READ_RMINC_OPCODE, dst, base);
- oneShortOp(opc);
- }
-
- void movlR0mr(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVL_READ_R0RM_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movlRegMemr0(RegisterID src, RegisterID dst)
- {
- uint16_t opc = getOpcodeGroup1(MOVL_WRITE_R0RN_OPCODE, dst, src);
- oneShortOp(opc);
- }
-
- void movlImm8r(int imm8, RegisterID dst)
- {
- ASSERT((imm8 <= 127) && (imm8 >= -128));
-
- uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, imm8);
- oneShortOp(opc);
- }
-
- void loadConstant(uint32_t constant, RegisterID dst)
- {
- if (((int)constant <= 0x7f) && ((int)constant >= -0x80)) {
- movImm8(constant, dst);
- return;
- }
-
- uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, 0);
-
- m_buffer.ensureSpace(maxInstructionSize, sizeof(uint32_t));
- printInstr(getOpcodeGroup3(MOVIMM_OPCODE, dst, constant), m_buffer.codeSize());
- m_buffer.putShortWithConstantInt(opc, constant, true);
- }
-
- void loadConstantUnReusable(uint32_t constant, RegisterID dst, bool ensureSpace = false)
- {
- uint16_t opc = getOpcodeGroup3(MOVIMM_OPCODE, dst, 0);
-
- if (ensureSpace)
- m_buffer.ensureSpace(maxInstructionSize, sizeof(uint32_t));
-
- printInstr(getOpcodeGroup3(MOVIMM_OPCODE, dst, constant), m_buffer.codeSize());
- m_buffer.putShortWithConstantInt(opc, constant);
- }
-
- // Flow control
-
- AssemblerLabel call()
- {
- RegisterID scr = claimScratch();
- m_buffer.ensureSpace(maxInstructionSize + 4, sizeof(uint32_t));
- loadConstantUnReusable(0x0, scr);
- branch(JSR_OPCODE, scr);
- nop();
- releaseScratch(scr);
- return m_buffer.label();
- }
-
- AssemblerLabel call(RegisterID dst)
- {
- m_buffer.ensureSpace(maxInstructionSize + 2);
- branch(JSR_OPCODE, dst);
- nop();
- return m_buffer.label();
- }
-
- AssemblerLabel jmp()
- {
- RegisterID scr = claimScratch();
- m_buffer.ensureSpace(maxInstructionSize + 4, sizeof(uint32_t));
- AssemblerLabel label = m_buffer.label();
- loadConstantUnReusable(0x0, scr);
- branch(BRAF_OPCODE, scr);
- nop();
- releaseScratch(scr);
- return label;
- }
-
- void extraInstrForBranch(RegisterID dst)
- {
- loadConstantUnReusable(0x0, dst);
- nop();
- nop();
- }
-
- AssemblerLabel jmp(RegisterID dst)
- {
- jmpReg(dst);
- return m_buffer.label();
- }
-
- void jmpReg(RegisterID dst)
- {
- m_buffer.ensureSpace(maxInstructionSize + 2);
- branch(JMP_OPCODE, dst);
- nop();
- }
-
- AssemblerLabel jne()
- {
- AssemblerLabel label = m_buffer.label();
- branch(BF_OPCODE, 0);
- return label;
- }
-
- AssemblerLabel je()
- {
- AssemblerLabel label = m_buffer.label();
- branch(BT_OPCODE, 0);
- return label;
- }
-
- AssemblerLabel bra()
- {
- AssemblerLabel label = m_buffer.label();
- branch(BRA_OPCODE, 0);
- return label;
- }
-
- void ret()
- {
- m_buffer.ensureSpace(maxInstructionSize + 2);
- oneShortOp(RTS_OPCODE, false);
- }
-
- AssemblerLabel labelIgnoringWatchpoints()
- {
- m_buffer.ensureSpaceForAnyInstruction();
- return m_buffer.label();
- }
-
- AssemblerLabel label()
- {
- m_buffer.ensureSpaceForAnyInstruction();
- return m_buffer.label();
- }
-
- int sizeOfConstantPool()
- {
- return m_buffer.sizeOfConstantPool();
- }
-
- AssemblerLabel align(int alignment)
- {
- m_buffer.ensureSpace(maxInstructionSize + 2);
- while (!m_buffer.isAligned(alignment)) {
- nop();
- m_buffer.ensureSpace(maxInstructionSize + 2);
- }
- return label();
- }
-
- static void changePCrelativeAddress(int offset, uint16_t* instructionPtr, uint32_t newAddress)
- {
- uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3));
- *reinterpret_cast<uint32_t*>(address) = newAddress;
- }
-
- static uint32_t readPCrelativeAddress(int offset, uint16_t* instructionPtr)
- {
- uint32_t address = (offset << 2) + ((reinterpret_cast<uint32_t>(instructionPtr) + 4) &(~0x3));
- return *reinterpret_cast<uint32_t*>(address);
- }
-
- static uint16_t* getInstructionPtr(void* code, int offset)
- {
- return reinterpret_cast<uint16_t*> (reinterpret_cast<uint32_t>(code) + offset);
- }
-
- static void linkJump(void* code, AssemblerLabel from, void* to)
- {
- ASSERT(from.isSet());
-
- uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset);
- uint16_t instruction = *instructionPtr;
- int offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(code)) - from.m_offset;
-
- if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
- /* BT label ==> BF 2
- nop LDR reg
- nop braf @reg
- nop nop
- */
- offsetBits -= 8;
- instruction ^= 0x0202;
- *instructionPtr++ = instruction;
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
- instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
- *instructionPtr = instruction;
- printBlockInstr(instructionPtr - 2, from.m_offset, 3);
- return;
- }
-
- /* MOV #imm, reg => LDR reg
- braf @reg braf @reg
- nop nop
- */
- ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
-
- offsetBits -= 4;
- if (offsetBits >= -4096 && offsetBits <= 4094) {
- *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
- *(++instructionPtr) = NOP_OPCODE;
- printBlockInstr(instructionPtr - 1, from.m_offset, 2);
- return;
- }
-
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
- printInstr(*instructionPtr, from.m_offset + 2);
- }
-
- static void linkCall(void* code, AssemblerLabel from, void* to)
- {
- uint16_t* instructionPtr = getInstructionPtr(code, from.m_offset);
- instructionPtr -= 3;
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to));
- }
-
- static void linkPointer(void* code, AssemblerLabel where, void* value)
- {
- uint16_t* instructionPtr = getInstructionPtr(code, where.m_offset);
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(value));
- }
-
- static unsigned getCallReturnOffset(AssemblerLabel call)
- {
- ASSERT(call.isSet());
- return call.m_offset;
- }
-
- static uint32_t* getLdrImmAddressOnPool(SH4Word* insn, uint32_t* constPool)
- {
- return (constPool + (*insn & 0xff));
- }
-
- static SH4Word patchConstantPoolLoad(SH4Word load, int value)
- {
- return ((load & ~0xff) | value);
- }
-
- static SH4Buffer::TwoShorts placeConstantPoolBarrier(int offset)
- {
- ASSERT(((offset >> 1) <=2047) && ((offset >> 1) >= -2048));
-
- SH4Buffer::TwoShorts m_barrier;
- m_barrier.high = (BRA_OPCODE | (offset >> 1));
- m_barrier.low = NOP_OPCODE;
- printInstr(((BRA_OPCODE | (offset >> 1))), 0);
- printInstr(NOP_OPCODE, 0);
- return m_barrier;
- }
-
- static void patchConstantPoolLoad(void* loadAddr, void* constPoolAddr)
- {
- SH4Word* instructionPtr = reinterpret_cast<SH4Word*>(loadAddr);
- SH4Word instruction = *instructionPtr;
- SH4Word index = instruction & 0xff;
-
- if ((instruction & 0xf000) != MOVIMM_OPCODE)
- return;
-
- ASSERT((((reinterpret_cast<uint32_t>(constPoolAddr) - reinterpret_cast<uint32_t>(loadAddr)) + index * 4)) < 1024);
-
- int offset = reinterpret_cast<uint32_t>(constPoolAddr) + (index * 4) - ((reinterpret_cast<uint32_t>(instructionPtr) & ~0x03) + 4);
- instruction &=0xf00;
- instruction |= 0xd000;
- offset &= 0x03ff;
- instruction |= (offset >> 2);
- *instructionPtr = instruction;
- printInstr(instruction, reinterpret_cast<uint32_t>(loadAddr));
- }
-
- static void repatchPointer(void* where, void* value)
- {
- patchPointer(where, value);
- }
-
- static void* readPointer(void* code)
- {
- return reinterpret_cast<void*>(readInt32(code));
- }
-
- static void repatchInt32(void* where, int32_t value)
- {
- uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(where);
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, value);
- }
-
- static void repatchCompact(void* where, int32_t value)
- {
- ASSERT(value >= 0);
- ASSERT(value <= 60);
- *reinterpret_cast<uint16_t*>(where) = ((*reinterpret_cast<uint16_t*>(where) & 0xfff0) | (value >> 2));
- cacheFlush(reinterpret_cast<uint16_t*>(where), sizeof(uint16_t));
- }
-
- static void relinkCall(void* from, void* to)
- {
- uint16_t* instructionPtr = reinterpret_cast<uint16_t*>(from);
- instructionPtr -= 3;
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, reinterpret_cast<uint32_t>(to));
- }
-
- static void relinkJump(void* from, void* to)
- {
- uint16_t* instructionPtr = reinterpret_cast<uint16_t*> (from);
- uint16_t instruction = *instructionPtr;
- int32_t offsetBits = (reinterpret_cast<uint32_t>(to) - reinterpret_cast<uint32_t>(from));
-
- if (((*instructionPtr & 0xff00) == BT_OPCODE) || ((*instructionPtr & 0xff00) == BF_OPCODE)) {
- offsetBits -= 8;
- instructionPtr++;
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
- instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
- *instructionPtr = instruction;
- printBlockInstr(instructionPtr, reinterpret_cast<uint32_t>(from) + 1, 3);
- return;
- }
-
- ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
- offsetBits -= 4;
- if (offsetBits >= -4096 && offsetBits <= 4094) {
- *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
- *(++instructionPtr) = NOP_OPCODE;
- printBlockInstr(instructionPtr - 2, reinterpret_cast<uint32_t>(from), 2);
- return;
- }
-
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
- printInstr(*instructionPtr, reinterpret_cast<uint32_t>(from));
- }
-
- // Linking & patching
-
- static void revertJump(void* instructionStart, SH4Word imm)
- {
- SH4Word *insn = reinterpret_cast<SH4Word*>(instructionStart);
- SH4Word disp;
-
- ASSERT((insn[0] & 0xf000) == MOVL_READ_OFFPC_OPCODE);
-
- disp = insn[0] & 0x00ff;
- insn += 2 + (disp << 1); // PC += 4 + (disp*4)
- insn = (SH4Word *) ((unsigned) insn & (~3));
- insn[0] = imm;
- cacheFlush(insn, sizeof(SH4Word));
- }
-
- void linkJump(AssemblerLabel from, AssemblerLabel to, JumpType type = JumpFar)
- {
- ASSERT(to.isSet());
- ASSERT(from.isSet());
-
- uint16_t* instructionPtr = getInstructionPtr(data(), from.m_offset);
- uint16_t instruction = *instructionPtr;
- int offsetBits;
-
- if (type == JumpNear) {
- ASSERT((instruction == BT_OPCODE) || (instruction == BF_OPCODE) || (instruction == BRA_OPCODE));
- int offset = (codeSize() - from.m_offset) - 4;
- *instructionPtr++ = instruction | (offset >> 1);
- printInstr(*instructionPtr, from.m_offset + 2);
- return;
- }
-
- if (((instruction & 0xff00) == BT_OPCODE) || ((instruction & 0xff00) == BF_OPCODE)) {
- /* BT label => BF 2
- nop LDR reg
- nop braf @reg
- nop nop
- */
- offsetBits = (to.m_offset - from.m_offset) - 8;
- instruction ^= 0x0202;
- *instructionPtr++ = instruction;
- if ((*instructionPtr & 0xf000) == 0xe000) {
- uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
- *addr = offsetBits;
- } else
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits);
- instruction = (BRAF_OPCODE | (*instructionPtr++ & 0xf00));
- *instructionPtr = instruction;
- printBlockInstr(instructionPtr - 2, from.m_offset, 3);
- return;
- }
-
- /* MOV # imm, reg => LDR reg
- braf @reg braf @reg
- nop nop
- */
- ASSERT((*(instructionPtr + 1) & BRAF_OPCODE) == BRAF_OPCODE);
- offsetBits = (to.m_offset - from.m_offset) - 4;
- if (offsetBits >= -4096 && offsetBits <= 4094) {
- *instructionPtr = getOpcodeGroup6(BRA_OPCODE, offsetBits >> 1);
- *(++instructionPtr) = NOP_OPCODE;
- printBlockInstr(instructionPtr - 1, from.m_offset, 2);
- return;
- }
-
- instruction = *instructionPtr;
- if ((instruction & 0xf000) == 0xe000) {
- uint32_t* addr = getLdrImmAddressOnPool(instructionPtr, m_buffer.poolAddress());
- *addr = offsetBits - 2;
- printInstr(*instructionPtr, from.m_offset + 2);
- return;
- }
-
- changePCrelativeAddress((*instructionPtr & 0xff), instructionPtr, offsetBits - 2);
- printInstr(*instructionPtr, from.m_offset + 2);
- }
-
- static void* getRelocatedAddress(void* code, AssemblerLabel label)
- {
- return reinterpret_cast<void*>(reinterpret_cast<char*>(code) + label.m_offset);
- }
-
- static int getDifferenceBetweenLabels(AssemblerLabel a, AssemblerLabel b)
- {
- return b.m_offset - a.m_offset;
- }
-
- static void patchPointer(void* code, AssemblerLabel where, void* value)
- {
- patchPointer(reinterpret_cast<uint32_t*>(code) + where.m_offset, value);
- }
-
- static void patchPointer(void* code, void* value)
- {
- patchInt32(code, reinterpret_cast<uint32_t>(value));
- }
-
- static void patchInt32(void* code, uint32_t value)
- {
- changePCrelativeAddress((*(reinterpret_cast<uint16_t*>(code)) & 0xff), reinterpret_cast<uint16_t*>(code), value);
- }
-
- static uint32_t readInt32(void* code)
- {
- return readPCrelativeAddress((*(reinterpret_cast<uint16_t*>(code)) & 0xff), reinterpret_cast<uint16_t*>(code));
- }
-
- static void* readCallTarget(void* from)
- {
- uint16_t* instructionPtr = static_cast<uint16_t*>(from);
- instructionPtr -= 3;
- return reinterpret_cast<void*>(readPCrelativeAddress((*instructionPtr & 0xff), instructionPtr));
- }
-
- PassRefPtr<ExecutableMemoryHandle> executableCopy(JSGlobalData& globalData, void* ownerUID, JITCompilationEffort effort)
- {
- return m_buffer.executableCopy(globalData, ownerUID, effort);
- }
-
- static void cacheFlush(void* code, size_t size)
- {
-#if !OS(LINUX)
-#error "The cacheFlush support is missing on this platform."
-#elif defined CACHEFLUSH_D_L2
- syscall(__NR_cacheflush, reinterpret_cast<unsigned>(code), size, CACHEFLUSH_D_WB | CACHEFLUSH_I | CACHEFLUSH_D_L2);
-#else
- syscall(__NR_cacheflush, reinterpret_cast<unsigned>(code), size, CACHEFLUSH_D_WB | CACHEFLUSH_I);
-#endif
- }
-
- void prefix(uint16_t pre)
- {
- m_buffer.putByte(pre);
- }
-
- void oneShortOp(uint16_t opcode, bool checksize = true, bool isDouble = true)
- {
- printInstr(opcode, m_buffer.codeSize(), isDouble);
- if (checksize)
- m_buffer.ensureSpace(maxInstructionSize);
- m_buffer.putShortUnchecked(opcode);
- }
-
- void ensureSpace(int space)
- {
- m_buffer.ensureSpace(space);
- }
-
- void ensureSpace(int insnSpace, int constSpace)
- {
- m_buffer.ensureSpace(insnSpace, constSpace);
- }
-
- // Administrative methods
-
- void* data() const { return m_buffer.data(); }
- size_t codeSize() const { return m_buffer.codeSize(); }
-
-#ifdef SH4_ASSEMBLER_TRACING
- static void printInstr(uint16_t opc, unsigned size, bool isdoubleInst = true)
- {
- if (!getenv("JavaScriptCoreDumpJIT"))
- return;
-
- const char *format = 0;
- printfStdoutInstr("offset: 0x%8.8x\t", size);
- switch (opc) {
- case BRK_OPCODE:
- format = " BRK\n";
- break;
- case NOP_OPCODE:
- format = " NOP\n";
- break;
- case RTS_OPCODE:
- format =" *RTS\n";
- break;
- case SETS_OPCODE:
- format = " SETS\n";
- break;
- case SETT_OPCODE:
- format = " SETT\n";
- break;
- case CLRT_OPCODE:
- format = " CLRT\n";
- break;
- case FSCHG_OPCODE:
- format = " FSCHG\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format);
- return;
- }
- switch (opc & 0xf0ff) {
- case BRAF_OPCODE:
- format = " *BRAF R%d\n";
- break;
- case DT_OPCODE:
- format = " DT R%d\n";
- break;
- case CMPPL_OPCODE:
- format = " CMP/PL R%d\n";
- break;
- case CMPPZ_OPCODE:
- format = " CMP/PZ R%d\n";
- break;
- case JMP_OPCODE:
- format = " *JMP @R%d\n";
- break;
- case JSR_OPCODE:
- format = " *JSR @R%d\n";
- break;
- case LDSPR_OPCODE:
- format = " LDS R%d, PR\n";
- break;
- case LDSLPR_OPCODE:
- format = " LDS.L @R%d+, PR\n";
- break;
- case MOVT_OPCODE:
- format = " MOVT R%d\n";
- break;
- case SHAL_OPCODE:
- format = " SHAL R%d\n";
- break;
- case SHAR_OPCODE:
- format = " SHAR R%d\n";
- break;
- case SHLL_OPCODE:
- format = " SHLL R%d\n";
- break;
- case SHLL2_OPCODE:
- format = " SHLL2 R%d\n";
- break;
- case SHLL8_OPCODE:
- format = " SHLL8 R%d\n";
- break;
- case SHLL16_OPCODE:
- format = " SHLL16 R%d\n";
- break;
- case SHLR_OPCODE:
- format = " SHLR R%d\n";
- break;
- case SHLR2_OPCODE:
- format = " SHLR2 R%d\n";
- break;
- case SHLR8_OPCODE:
- format = " SHLR8 R%d\n";
- break;
- case SHLR16_OPCODE:
- format = " SHLR16 R%d\n";
- break;
- case STSPR_OPCODE:
- format = " STS PR, R%d\n";
- break;
- case STSLPR_OPCODE:
- format = " STS.L PR, @-R%d\n";
- break;
- case LDS_RM_FPUL_OPCODE:
- format = " LDS R%d, FPUL\n";
- break;
- case STS_FPUL_RN_OPCODE:
- format = " STS FPUL, R%d \n";
- break;
- case FLDS_FRM_FPUL_OPCODE:
- format = " FLDS FR%d, FPUL\n";
- break;
- case FSTS_FPUL_FRN_OPCODE:
- format = " FSTS FPUL, R%d \n";
- break;
- case LDSFPSCR_OPCODE:
- format = " LDS R%d, FPSCR \n";
- break;
- case STSFPSCR_OPCODE:
- format = " STS FPSCR, R%d \n";
- break;
- case STSMACL_OPCODE:
- format = " STS MACL, R%d \n";
- break;
- case STSMACH_OPCODE:
- format = " STS MACH, R%d \n";
- break;
- case BSRF_OPCODE:
- format = " *BSRF R%d";
- break;
- case FTRC_OPCODE:
- format = " FTRC FR%d, FPUL\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getRn(opc));
- return;
- }
- switch (opc & 0xf0ff) {
- case FNEG_OPCODE:
- format = " FNEG DR%d\n";
- break;
- case FLOAT_OPCODE:
- format = " FLOAT DR%d\n";
- break;
- case FTRC_OPCODE:
- format = " FTRC FR%d, FPUL\n";
- break;
- case FSQRT_OPCODE:
- format = " FSQRT FR%d\n";
- break;
- case FCNVDS_DRM_FPUL_OPCODE:
- format = " FCNVDS FR%d, FPUL\n";
- break;
- case FCNVSD_FPUL_DRN_OPCODE:
- format = " FCNVSD FPUL, FR%d\n";
- break;
- }
- if (format) {
- if (isdoubleInst)
- printfStdoutInstr(format, getDRn(opc) << 1);
- else
- printfStdoutInstr(format, getRn(opc));
- return;
- }
- switch (opc & 0xf00f) {
- case ADD_OPCODE:
- format = " ADD R%d, R%d\n";
- break;
- case ADDC_OPCODE:
- format = " ADDC R%d, R%d\n";
- break;
- case ADDV_OPCODE:
- format = " ADDV R%d, R%d\n";
- break;
- case AND_OPCODE:
- format = " AND R%d, R%d\n";
- break;
- case DIV1_OPCODE:
- format = " DIV1 R%d, R%d\n";
- break;
- case CMPEQ_OPCODE:
- format = " CMP/EQ R%d, R%d\n";
- break;
- case CMPGE_OPCODE:
- format = " CMP/GE R%d, R%d\n";
- break;
- case CMPGT_OPCODE:
- format = " CMP/GT R%d, R%d\n";
- break;
- case CMPHI_OPCODE:
- format = " CMP/HI R%d, R%d\n";
- break;
- case CMPHS_OPCODE:
- format = " CMP/HS R%d, R%d\n";
- break;
- case MOV_OPCODE:
- format = " MOV R%d, R%d\n";
- break;
- case MOVB_WRITE_RN_OPCODE:
- format = " MOV.B R%d, @R%d\n";
- break;
- case MOVB_WRITE_RNDEC_OPCODE:
- format = " MOV.B R%d, @-R%d\n";
- break;
- case MOVB_WRITE_R0RN_OPCODE:
- format = " MOV.B R%d, @(R0, R%d)\n";
- break;
- case MOVB_READ_RM_OPCODE:
- format = " MOV.B @R%d, R%d\n";
- break;
- case MOVB_READ_RMINC_OPCODE:
- format = " MOV.B @R%d+, R%d\n";
- break;
- case MOVB_READ_R0RM_OPCODE:
- format = " MOV.B @(R0, R%d), R%d\n";
- break;
- case MOVL_WRITE_RN_OPCODE:
- format = " MOV.L R%d, @R%d\n";
- break;
- case MOVL_WRITE_RNDEC_OPCODE:
- format = " MOV.L R%d, @-R%d\n";
- break;
- case MOVL_WRITE_R0RN_OPCODE:
- format = " MOV.L R%d, @(R0, R%d)\n";
- break;
- case MOVL_READ_RM_OPCODE:
- format = " MOV.L @R%d, R%d\n";
- break;
- case MOVL_READ_RMINC_OPCODE:
- format = " MOV.L @R%d+, R%d\n";
- break;
- case MOVL_READ_R0RM_OPCODE:
- format = " MOV.L @(R0, R%d), R%d\n";
- break;
- case MULL_OPCODE:
- format = " MUL.L R%d, R%d\n";
- break;
- case DMULL_L_OPCODE:
- format = " DMULU.L R%d, R%d\n";
- break;
- case DMULSL_OPCODE:
- format = " DMULS.L R%d, R%d\n";
- break;
- case NEG_OPCODE:
- format = " NEG R%d, R%d\n";
- break;
- case NEGC_OPCODE:
- format = " NEGC R%d, R%d\n";
- break;
- case NOT_OPCODE:
- format = " NOT R%d, R%d\n";
- break;
- case OR_OPCODE:
- format = " OR R%d, R%d\n";
- break;
- case SHAD_OPCODE:
- format = " SHAD R%d, R%d\n";
- break;
- case SHLD_OPCODE:
- format = " SHLD R%d, R%d\n";
- break;
- case SUB_OPCODE:
- format = " SUB R%d, R%d\n";
- break;
- case SUBC_OPCODE:
- format = " SUBC R%d, R%d\n";
- break;
- case SUBV_OPCODE:
- format = " SUBV R%d, R%d\n";
- break;
- case TST_OPCODE:
- format = " TST R%d, R%d\n";
- break;
- case XOR_OPCODE:
- format = " XOR R%d, R%d\n";break;
- case MOVW_WRITE_RN_OPCODE:
- format = " MOV.W R%d, @R%d\n";
- break;
- case MOVW_READ_RM_OPCODE:
- format = " MOV.W @R%d, R%d\n";
- break;
- case MOVW_READ_R0RM_OPCODE:
- format = " MOV.W @(R0, R%d), R%d\n";
- break;
- case EXTUB_OPCODE:
- format = " EXTU.B R%d, R%d\n";
- break;
- case EXTUW_OPCODE:
- format = " EXTU.W R%d, R%d\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getRm(opc), getRn(opc));
- return;
- }
- switch (opc & 0xf00f) {
- case FSUB_OPCODE:
- format = " FSUB FR%d, FR%d\n";
- break;
- case FADD_OPCODE:
- format = " FADD FR%d, FR%d\n";
- break;
- case FDIV_OPCODE:
- format = " FDIV FR%d, FR%d\n";
- break;
- case FMUL_OPCODE:
- format = " DMULL FR%d, FR%d\n";
- break;
- case FMOV_OPCODE:
- format = " FMOV FR%d, FR%d\n";
- break;
- case FCMPEQ_OPCODE:
- format = " FCMP/EQ FR%d, FR%d\n";
- break;
- case FCMPGT_OPCODE:
- format = " FCMP/GT FR%d, FR%d\n";
- break;
- }
- if (format) {
- if (isdoubleInst)
- printfStdoutInstr(format, getDRm(opc) << 1, getDRn(opc) << 1);
- else
- printfStdoutInstr(format, getRm(opc), getRn(opc));
- return;
- }
- switch (opc & 0xf00f) {
- case FMOVS_WRITE_RN_DEC_OPCODE:
- format = " %s FR%d, @-R%d\n";
- break;
- case FMOVS_WRITE_RN_OPCODE:
- format = " %s FR%d, @R%d\n";
- break;
- case FMOVS_WRITE_R0RN_OPCODE:
- format = " %s FR%d, @(R0, R%d)\n";
- break;
- }
- if (format) {
- if (isdoubleInst)
- printfStdoutInstr(format, "FMOV", getDRm(opc) << 1, getDRn(opc));
- else
- printfStdoutInstr(format, "FMOV.S", getRm(opc), getRn(opc));
- return;
- }
- switch (opc & 0xf00f) {
- case FMOVS_READ_RM_OPCODE:
- format = " %s @R%d, FR%d\n";
- break;
- case FMOVS_READ_RM_INC_OPCODE:
- format = " %s @R%d+, FR%d\n";
- break;
- case FMOVS_READ_R0RM_OPCODE:
- format = " %s @(R0, R%d), FR%d\n";
- break;
- }
- if (format) {
- if (isdoubleInst)
- printfStdoutInstr(format, "FMOV", getDRm(opc), getDRn(opc) << 1);
- else
- printfStdoutInstr(format, "FMOV.S", getRm(opc), getRn(opc));
- return;
- }
- switch (opc & 0xff00) {
- case BF_OPCODE:
- format = " BF %d\n";
- break;
- case BFS_OPCODE:
- format = " *BF/S %d\n";
- break;
- case ANDIMM_OPCODE:
- format = " AND #%d, R0\n";
- break;
- case BT_OPCODE:
- format = " BT %d\n";
- break;
- case BTS_OPCODE:
- format = " *BT/S %d\n";
- break;
- case CMPEQIMM_OPCODE:
- format = " CMP/EQ #%d, R0\n";
- break;
- case MOVB_WRITE_OFFGBR_OPCODE:
- format = " MOV.B R0, @(%d, GBR)\n";
- break;
- case MOVB_READ_OFFGBR_OPCODE:
- format = " MOV.B @(%d, GBR), R0\n";
- break;
- case MOVL_WRITE_OFFGBR_OPCODE:
- format = " MOV.L R0, @(%d, GBR)\n";
- break;
- case MOVL_READ_OFFGBR_OPCODE:
- format = " MOV.L @(%d, GBR), R0\n";
- break;
- case MOVA_READ_OFFPC_OPCODE:
- format = " MOVA @(%d, PC), R0\n";
- break;
- case ORIMM_OPCODE:
- format = " OR #%d, R0\n";
- break;
- case ORBIMM_OPCODE:
- format = " OR.B #%d, @(R0, GBR)\n";
- break;
- case TSTIMM_OPCODE:
- format = " TST #%d, R0\n";
- break;
- case TSTB_OPCODE:
- format = " TST.B %d, @(R0, GBR)\n";
- break;
- case XORIMM_OPCODE:
- format = " XOR #%d, R0\n";
- break;
- case XORB_OPCODE:
- format = " XOR.B %d, @(R0, GBR)\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getImm8(opc));
- return;
- }
- switch (opc & 0xff00) {
- case MOVB_WRITE_OFFRN_OPCODE:
- format = " MOV.B R0, @(%d, R%d)\n";
- break;
- case MOVB_READ_OFFRM_OPCODE:
- format = " MOV.B @(%d, R%d), R0\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getDisp(opc), getRm(opc));
- return;
- }
- switch (opc & 0xf000) {
- case BRA_OPCODE:
- format = " *BRA %d\n";
- break;
- case BSR_OPCODE:
- format = " *BSR %d\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getImm12(opc));
- return;
- }
- switch (opc & 0xf000) {
- case MOVL_READ_OFFPC_OPCODE:
- format = " MOV.L @(%d, PC), R%d\n";
- break;
- case ADDIMM_OPCODE:
- format = " ADD #%d, R%d\n";
- break;
- case MOVIMM_OPCODE:
- format = " MOV #%d, R%d\n";
- break;
- case MOVW_READ_OFFPC_OPCODE:
- format = " MOV.W @(%d, PC), R%d\n";
- break;
- }
- if (format) {
- printfStdoutInstr(format, getImm8(opc), getRn(opc));
- return;
- }
- switch (opc & 0xf000) {
- case MOVL_WRITE_OFFRN_OPCODE:
- format = " MOV.L R%d, @(%d, R%d)\n";
- printfStdoutInstr(format, getRm(opc), getDisp(opc), getRn(opc));
- break;
- case MOVL_READ_OFFRM_OPCODE:
- format = " MOV.L @(%d, R%d), R%d\n";
- printfStdoutInstr(format, getDisp(opc), getRm(opc), getRn(opc));
- break;
- }
- }
-
- static void printfStdoutInstr(const char* format, ...)
- {
- if (getenv("JavaScriptCoreDumpJIT")) {
- va_list args;
- va_start(args, format);
- vprintfStdoutInstr(format, args);
- va_end(args);
- }
- }
-
- static void vprintfStdoutInstr(const char* format, va_list args)
- {
- if (getenv("JavaScriptCoreDumpJIT"))
- WTF::dataLogFV(format, args);
- }
-
- static void printBlockInstr(uint16_t* first, unsigned offset, int nbInstr)
- {
- printfStdoutInstr(">> repatch instructions after link\n");
- for (int i = 0; i <= nbInstr; i++)
- printInstr(*(first + i), offset + i);
- printfStdoutInstr(">> end repatch\n");
- }
-#else
- static void printInstr(uint16_t opc, unsigned size, bool isdoubleInst = true) { };
- static void printBlockInstr(uint16_t* first, unsigned offset, int nbInstr) { };
-#endif
-
- static void replaceWithLoad(void* instructionStart)
- {
- SH4Word* insPtr = reinterpret_cast<SH4Word*>(instructionStart);
-
- insPtr += 2; // skip MOV and ADD opcodes
-
- if (((*insPtr) & 0xf00f) != MOVL_READ_RM_OPCODE) {
- *insPtr = MOVL_READ_RM_OPCODE | (*insPtr & 0x0ff0);
- cacheFlush(insPtr, sizeof(SH4Word));
- }
- }
-
- static void replaceWithAddressComputation(void* instructionStart)
- {
- SH4Word* insPtr = reinterpret_cast<SH4Word*>(instructionStart);
-
- insPtr += 2; // skip MOV and ADD opcodes
-
- if (((*insPtr) & 0xf00f) != MOV_OPCODE) {
- *insPtr = MOV_OPCODE | (*insPtr & 0x0ff0);
- cacheFlush(insPtr, sizeof(SH4Word));
- }
- }
-
-private:
- SH4Buffer m_buffer;
- int m_claimscratchReg;
-};
-
-} // namespace JSC
-
-#endif // ENABLE(ASSEMBLER) && CPU(SH4)
-
-#endif // SH4Assembler_h
diff --git a/src/3rdparty/masm/wtf/Platform.h b/src/3rdparty/masm/wtf/Platform.h
index d10a60e642..81f79f7084 100644
--- a/src/3rdparty/masm/wtf/Platform.h
+++ b/src/3rdparty/masm/wtf/Platform.h
@@ -741,10 +741,6 @@
#define ENABLE_JIT 0
#endif
-#if !defined(ENABLE_JIT) && CPU(SH4) && PLATFORM(QT)
-#define ENABLE_JIT 1
-#endif
-
/* The JIT is enabled by default on all x86, x86-64, ARM & MIPS platforms. */
#if !defined(ENABLE_JIT) \
&& (CPU(X86) || CPU(X86_64) || CPU(ARM) || CPU(MIPS) || CPU(ARM64)) \