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path: root/src/3rdparty/masm/assembler/MacroAssemblerARMv7.h
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* Remove the bootstrap code from assembler and JITUlf Hermann2019-05-071-70/+1
| | | | | | | We don't build the assembler or the JIT in bootstrap mode. Change-Id: Idc3a56cc1e9cfba415bef9cba221c8a60ee75010 Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* Update Yarr to the latest version from WebKitLars Knoll2018-08-101-0/+13
| | | | | | | | | | | Updated Yarr to a to commit 4d2a53d60487cb1f8b2a9a1e9f684af336fd7d2c in WebKit. Adjusted the yarr code base to work with our older version of wtf and masm. Change-Id: I04b4593ece051e1d7aa087b87aa08c92595d1098 Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* V4: Add a baseline JITErik Verbruggen2017-11-171-0/+11
| | | | | | | | This patch add a JIT back in for all platforms that supported JITting before, with the exception of MIPS. Change-Id: I51bc5ce3a2ac40e0510bd72a563af897c5b60343 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Fix stack pointer arithmetic when cross-compilingSimon Hausmann2017-03-291-0/+2
| | | | | | | | | | Replace the use of size(void*) with target assembler specific values for the pointer size, when calculating offsets into the stack for poke/peek/push/pop and placing arguments onto the stack before calling functions. Change-Id: I3aff540f0083967e75b61e0c29dbeb4d9ecfa433 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Fix pop(RegisterID) on ARMv7 when cross-compilingSimon Hausmann2017-03-291-1/+1
| | | | | | | | | This is implemented as ldr instruction that automatically adjusts the indexing register, which for ARMv7 needs to be always 4-bytes, not sizeof(void*) which can be 8 on 64-bit hosts. Change-Id: I66cce2a7388ef12b321db643e8efb002158519aa Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Include the ARMv7 assembler in the qmldevtools bootstrap buildSimon Hausmann2017-02-011-6/+73
| | | | | | | | | | | | | | | | | | | | | | | | | Even when the C++ target is not ARMv7 we want to include it in order to be able to generate QML cache files with code ahead of time. This requires a few changes: * The Jump classes need to move from the AbstractMacroAssembler super-class into the concrete assembler sub-class, in order to use it in specializations. * Some of the template specializations in LinkBuffer for example or for platform dependent operations need to be pre-processor enabled when bootstrapping * The generic loadPtr/addPtr etc. functions need to move to the concrete assemblers to be able to call the correct 32-bit or 64-bit variations. * We need to force what looks like a loss of precision to the compiler in the 32-bit ARMv7 linking code when linking jumps. Finally then we can explicitly instantiate at least QV4::JIT::Assembler for ARMv7 when bootstrapping. Currently only on x86-64 hosts, but that is a temporary limitation. Change-Id: I501db2360e1fded48f17f17d9e87252d47f8537e Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* Remove branch compaction #ifdefSimon Hausmann2017-01-311-1/+1
| | | | | | | | | | | | | Since the #ifdef for ARMv7 and ARM64 makes it impossible to cross compile, we need to replace it with a template specialization of LinkBuffer. The "old" LinkBuffer becomes LinkBufferBase, then there's a generic LinkBuffer that's a sub-class of LinkBufferBase. Then there's a BranchCompactingLinkBuffer template that implements the compaction and two ARMv7 and ARM64 specializations of LinkBuffer<T> end up being sub-classes of BranchCompactingLinkBuffer instead of LinkBufferBase. Change-Id: Ib62fe24aa6c3570dfa311edc39fde6fb5975f3cc Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Changed JSC::MacroAssembler to be a templateSimon Hausmann2017-01-281-1/+4
| | | | | Change-Id: If6edb7ed0fac51e93b218eb45c01274a87b9e904 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Make JSC::LinkBuffer a templateSimon Hausmann2017-01-281-1/+1
| | | | | | | Unfortunately the link buffer depends on target platform types. Change-Id: Idb49e72e8e864c709293a7b315dff948bc58e62a Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* V4: add Aarch64/ARM64 support.Erik Verbruggen2016-01-191-1/+1
| | | | | | | | | | This uses the JavaScriptCore assembler rev. 195098. It is tested on iOS (for which it is disabled, as it only allows marking pages as executable when running from Xcode). Testing on Linux will be done when hardware arrives. Change-Id: I650e15fec03c27d4b326a2d70863a89b85cfc5c3 Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* V4 JIT: ARM: move registers around.Erik Verbruggen2015-01-121-1/+1
| | | | | | | | | | | | | | | | In 6572d4e50d73ac60a8974d07de74c27a7f99ebef we moved the addressTempRegister to r10, and in d8b276a59402cbbe6d070ba38805350e7f3dd8a1 we made sure that the YarrJIT saves it too. JSC solved this by moving it to r6, which is already saved by the YarrJIT. To make a future update of the assembler easier, we also move it to r6. This requires that we move our scratch register too. But, because it is used a lot, we don't want it above r7 for Thumb2 reasons. Therefore, we move the engine to r10, and the scratch register to r5. Change-Id: I35be539940d9fe80971973cfa7f3a8dab2196a1e Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: tune generated instructions for inplace binopsErik Verbruggen2014-08-121-0/+18
| | | | | | | | | | Generate better code for in-place binary operations where the right-hand side is either a constant or a memory address. Now that the JIT can do this, also tell the register allocator not to un-spill that right-hand side. Change-Id: I0ab852f6b92f90dfed99c05fbaf91aad2549ecf4 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: enable the JIT when compiling with clang on ARM.Erik Verbruggen2014-07-241-0/+1
| | | | | | | | The macros that were used to detect Thumb2 support on the cores were gcc specific. Change-Id: I76959899b41f440d4b7ad7a5436059a3dc102111 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4: fix register usage on ARM.Erik Verbruggen2014-04-171-1/+1
| | | | | | | | | | | JSC was using r3 as the address scratch register, which collides with the 4th parameter in a function call. This sometimes shows up when generateFunctionCall needs to do a calulated jump. Also fix the usage of r11, which seems to be the fp on some platforms. Change-Id: Ib2ea64b9342e5aa631db6a7641747f899b2fbd89 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 IR: reverse propagate int32 truncation.Erik Verbruggen2013-12-041-0/+10
| | | | | Change-Id: I5cb0c7798d0e530f3137710bf0e723bd7b64dc89 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: implement convertUInt32ToDouble on ARMv7.Erik Verbruggen2013-10-031-0/+6
| | | | | Change-Id: I11caf07a8776bb2c6527639f22d47103f4ca1cef Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4 JIT: generate code for binary expressions.Erik Verbruggen2013-09-111-0/+6
| | | | | Change-Id: If32ee3528fa0b6a2d04263d6c6abe1d34053d658 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* WTF/JSC update to r148273Simon Hausmann2013-04-121-2/+13
| | | | | | | | | | | | | This brings in various bug fixes in the ARM and MIPS assemblers as well as a Yarr crash fix and performance fix. This change doesn't compile as-is, but the next change will apply the modifications necessary to compile. That'll make future updates easier as it allows for cherry-picking because the modifications are usually always the same. Change-Id: Iac32f62c71e8ff908deb41f28f12fbc98c0823e1 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Say hello to QtV4 module.Jędrzej Nowacki2013-01-301-0/+1903
Change-Id: I507cd5707b7d7223a0d901cf939896fb2649b684 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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