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* Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-06-063-21/+19
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: .qmake.conf src/qml/jsruntime/qv4argumentsobject.cpp src/qml/jsruntime/qv4arraydata.cpp src/qml/jsruntime/qv4context.cpp src/qml/jsruntime/qv4context_p.h src/qml/jsruntime/qv4errorobject.cpp src/qml/jsruntime/qv4functionobject.cpp src/qml/jsruntime/qv4internalclass.cpp src/qml/jsruntime/qv4lookup.cpp src/qml/jsruntime/qv4managed.cpp src/qml/jsruntime/qv4managed_p.h src/qml/jsruntime/qv4object.cpp src/qml/jsruntime/qv4object_p.h src/qml/jsruntime/qv4qmlcontext.cpp src/qml/jsruntime/qv4runtime.cpp src/qml/jsruntime/qv4vme_moth.cpp src/qml/memory/qv4heap_p.h src/qml/memory/qv4mm.cpp src/qml/memory/qv4mm_p.h src/qml/memory/qv4mmdefs_p.h src/quick/scenegraph/util/qsgdistancefieldutil.cpp src/quick/scenegraph/util/qsgdistancefieldutil_p.h tests/auto/qml/qqmllanguage/tst_qqmllanguage.cpp Change-Id: I7ed925d4f5d308f872a58ddf51fdce0c8494ec9c
| * Fix build on MIPS32Simon Hausmann2017-05-101-8/+0
| | | | | | | | | | | | | | | | Remove stack handling function that's dead code that doesn't compile. Task-number: QTBUG-58567 Change-Id: I704b0323522ce2a313d6cc85112f782872c3bf68 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
| * Fix crash in pre-cross-compiled ARMv7 code when host was 64-bitSimon Hausmann2017-05-041-8/+14
| | | | | | | | | | | | | | | | | | | | When encoding negative offsets for relative jumps, we must stay within signed 32-bit range to correctly perform all the different thumb offset encodings correctly. Task-number: QTBUG-60441 Change-Id: I0a7243debbcbc4d557710dddbd39cb97bd702da4 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
| * Fix ARM64 code generationSimon Hausmann2017-05-031-5/+5
| | | | | | | | | | | | | | | | | | | | When generating instructions for pointer arithmetic, do use the 64-bit registers, otherwise for example when loading pointers we'll end up only loading the lower 32 bits. Task-number: QTBUG-60441 Change-Id: I2c7c82964029e383afcadabc078842690d2d637a Reviewed-by: Robin Burchell <robin.burchell@crimson.no>
* | Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-03-306-5/+15
|\| | | | | | | | | | | | | | | Conflicts: src/qml/jit/qv4assembler.cpp src/qml/jit/qv4assembler_p.h Change-Id: Ibfe69610ccd1f275f181b2bd87feece4ba221e50
| * Fix stack pointer arithmetic when cross-compilingSimon Hausmann2017-03-296-4/+14
| | | | | | | | | | | | | | | | | | | | Replace the use of size(void*) with target assembler specific values for the pointer size, when calculating offsets into the stack for poke/peek/push/pop and placing arguments onto the stack before calling functions. Change-Id: I3aff540f0083967e75b61e0c29dbeb4d9ecfa433 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
| * Fix pop(RegisterID) on ARMv7 when cross-compilingSimon Hausmann2017-03-291-1/+1
| | | | | | | | | | | | | | | | | | This is implemented as ldr instruction that automatically adjusts the indexing register, which for ARMv7 needs to be always 4-bytes, not sizeof(void*) which can be 8 on 64-bit hosts. Change-Id: I66cce2a7388ef12b321db643e8efb002158519aa Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* | Merge remote-tracking branch 'origin/5.9' into devLiang Qi2017-03-141-0/+2
|\| | | | | | | Change-Id: I0ec164ce6e8099e6e4d6b40a3c7340737473ef4b
| * Fix build in clang5.0Jesus Fernandez2017-03-021-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Fixes: X86Assembler.h:281:19: error: 'm_assembler' is a protected member of 'JSC::AbstractMacroAssembler<JSC::X86Assembler>' masm->m_assembler.linkJump(m_label, masm->m_assembler.label()); AbstractMacroAssembler.h:819:19: note: declared protected here AssemblerType m_assembler; Change-Id: I04f6dc254e9826b9835a43b604a05ea4c57f661b Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* | Add missing 64 bit shift operations to the X64 macro assemblerLars Knoll2017-03-092-20/+73
|/ | | | | Change-Id: I1e593e5ed0bb24ed3a158d98495209945c8bb309 Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* Fix ARM64 buildSimon Hausmann2017-02-086-39/+156
| | | | | | | | | Add the ARM64 assembler to cross-compilation. Task-number: QTBUG-58568 Change-Id: I91461ebf79fb83e31e8ae2962ab0e155d308281a Reviewed-by: Qt CI Bot <qt_ci_bot@qt-project.org> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Include the ARMv7 assembler in the qmldevtools bootstrap buildSimon Hausmann2017-02-018-23/+281
| | | | | | | | | | | | | | | | | | | | | | | | | Even when the C++ target is not ARMv7 we want to include it in order to be able to generate QML cache files with code ahead of time. This requires a few changes: * The Jump classes need to move from the AbstractMacroAssembler super-class into the concrete assembler sub-class, in order to use it in specializations. * Some of the template specializations in LinkBuffer for example or for platform dependent operations need to be pre-processor enabled when bootstrapping * The generic loadPtr/addPtr etc. functions need to move to the concrete assemblers to be able to call the correct 32-bit or 64-bit variations. * We need to force what looks like a loss of precision to the compiler in the 32-bit ARMv7 linking code when linking jumps. Finally then we can explicitly instantiate at least QV4::JIT::Assembler for ARMv7 when bootstrapping. Currently only on x86-64 hosts, but that is a temporary limitation. Change-Id: I501db2360e1fded48f17f17d9e87252d47f8537e Reviewed-by: Simon Hausmann <simon.hausmann@qt.io>
* Bootstrap build fixSimon Hausmann2017-01-311-2/+5
| | | | | | | | Avoid the cache flushing code, it's of no use and won't compile due to the use of inline assembly. Change-Id: I1542b48f53f9210943bcf1f7cc5cc03f4abca695 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Remove branch compaction #ifdefSimon Hausmann2017-01-319-64/+155
| | | | | | | | | | | | | Since the #ifdef for ARMv7 and ARM64 makes it impossible to cross compile, we need to replace it with a template specialization of LinkBuffer. The "old" LinkBuffer becomes LinkBufferBase, then there's a generic LinkBuffer that's a sub-class of LinkBufferBase. Then there's a BranchCompactingLinkBuffer template that implements the compaction and two ARMv7 and ARM64 specializations of LinkBuffer<T> end up being sub-classes of BranchCompactingLinkBuffer instead of LinkBufferBase. Change-Id: Ib62fe24aa6c3570dfa311edc39fde6fb5975f3cc Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Changed JSC::MacroAssembler to be a templateSimon Hausmann2017-01-282-2/+34
| | | | | Change-Id: If6edb7ed0fac51e93b218eb45c01274a87b9e904 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Make JSC::LinkBuffer a templateSimon Hausmann2017-01-2810-164/+171
| | | | | | | Unfortunately the link buffer depends on target platform types. Change-Id: Idb49e72e8e864c709293a7b315dff948bc58e62a Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Cleanup MacroAssembler in preparation for becoming a templateSimon Hausmann2017-01-281-53/+74
| | | | | | | Move some of the used types and functions into the class name space. Change-Id: I2da72714d796a202ae9181c7a18745a94d95d925 Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Add initial support for INTEGRITYKimmo Ollila2017-01-131-1/+1
| | | | | | Change-Id: I1b44263a700f6c48c3b7798b662b30b03f9a4dc4 Reviewed-by: Rolland Dudemaine <rolland@ghs.com> Reviewed-by: Lars Knoll <lars.knoll@qt.io>
* Enable V4 JIT for aarch64Laszlo Agocs2016-02-011-1/+1
| | | | | | | | | | 64-bit ARM boards (f.ex. with Tegra X1) are becoming common and therefore enabling the JIT would be highly beneficial. Change-Id: I5ee46258151885194f93d2528edddd5f51dff964 Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com> Reviewed-by: Lars Knoll <lars.knoll@theqtcompany.com> Reviewed-by: Erik Verbruggen <erik.verbruggen@theqtcompany.com>
* V4: add Aarch64/ARM64 support.Erik Verbruggen2016-01-196-7/+7287
| | | | | | | | | | This uses the JavaScriptCore assembler rev. 195098. It is tested on iOS (for which it is disabled, as it only allows marking pages as executable when running from Xcode). Testing on Linux will be done when hardware arrives. Change-Id: I650e15fec03c27d4b326a2d70863a89b85cfc5c3 Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* V4: add JIT support for mips platforms (32-bit) and enable itJulien Brianceau2015-04-271-1/+31
| | | | | | | [ChangeLog][QtQml] Enabled Just-In-Time compilation for JavaScript on MIPS Change-Id: Idce070f29645760d6376767ef67e4592828c104d Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* Merge remote-tracking branch 'origin/5.4' into 5.5Liang Qi2015-04-161-2/+4
|\ | | | | | | | | | | | | | | Conflicts: tests/auto/qml/debugger/qv4profilerservice/qv4profilerservice.pro tests/auto/qml/debugger/qqmldebuggingenabler/qqmldebuggingenabler.pro Change-Id: I76d87e3df97ebdba902ca3d7488c1582eca2a83c
| * [mips] Fix or32 implementation in macro assembler.Julien Brianceau2015-04-071-1/+3
| | | | | | | | | | | | | | Cherry-picked from qtwebkit (0546c8656a3728bf4375da39027e096beba4f111) Change-Id: I924661dc51bee334c6f26557e765a3a1e8ec0bce Reviewed-by: Allan Sandfeld Jensen <allan.jensen@theqtcompany.com>
| * [mips] Fix branchTruncateDoubleToUint32 implementation in macro assembler.Julien Brianceau2015-04-071-1/+1
| | | | | | | | | | | | | | Cherry-picked from qtwebkit (2d9ed318a21f6102dddc0b91de2698908a9b8efc) Change-Id: I88d961e89d046b20329bc1fcfc10bfceb21d737b Reviewed-by: Allan Sandfeld Jensen <allan.jensen@theqtcompany.com>
* | [mips] Handle properly unaligned halfword load.Julien Brianceau2015-04-081-1/+47
| | | | | | | | | | | | | | | | | | This patch improves YarrJIT efficiency on mips platforms. Cherry-picked from qtwebkit (ea22657d17a934b04c8621dc8891a1d4d80510e3) Change-Id: I83eca9716e4d6e9e1dd4d8ceb76c3da380502ce7 Reviewed-by: Allan Sandfeld Jensen <allan.jensen@theqtcompany.com>
* | V4 JIT: ARM: move registers around.Erik Verbruggen2015-01-122-3/+3
|/ | | | | | | | | | | | | | | | In 6572d4e50d73ac60a8974d07de74c27a7f99ebef we moved the addressTempRegister to r10, and in d8b276a59402cbbe6d070ba38805350e7f3dd8a1 we made sure that the YarrJIT saves it too. JSC solved this by moving it to r6, which is already saved by the YarrJIT. To make a future update of the assembler easier, we also move it to r6. This requires that we move our scratch register too. But, because it is used a lot, we don't want it above r7 for Thumb2 reasons. Therefore, we move the engine to r10, and the scratch register to r5. Change-Id: I35be539940d9fe80971973cfa7f3a8dab2196a1e Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: tune generated instructions for inplace binopsErik Verbruggen2014-08-121-0/+18
| | | | | | | | | | Generate better code for in-place binary operations where the right-hand side is either a constant or a memory address. Now that the JIT can do this, also tell the register allocator not to un-spill that right-hand side. Change-Id: I0ab852f6b92f90dfed99c05fbaf91aad2549ecf4 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: enable the JIT when compiling with clang on ARM.Erik Verbruggen2014-07-241-0/+1
| | | | | | | | The macros that were used to detect Thumb2 support on the cores were gcc specific. Change-Id: I76959899b41f440d4b7ad7a5436059a3dc102111 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4: fix register usage on ARM.Erik Verbruggen2014-04-171-1/+1
| | | | | | | | | | | JSC was using r3 as the address scratch register, which collides with the 4th parameter in a function call. This sometimes shows up when generateFunctionCall needs to do a calulated jump. Also fix the usage of r11, which seems to be the fp on some platforms. Change-Id: Ib2ea64b9342e5aa631db6a7641747f899b2fbd89 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4: fix address printing on 64bit platformsErik Verbruggen2014-03-071-1/+7
| | | | | | | | The addresses were truncated to 32bits, which is a problem on win64, because JITted code ended up outside that range. Change-Id: I0d8b92486714340dffe4b4c2de29cf11a929a149 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Fix MSVC2012 compiler warnings in disabled code.Erik Verbruggen2014-03-071-1/+2
| | | | | | | ... that should soon get enabled. Change-Id: I2f8393cab5e99a7f5d3c7df6af6385fefd2d4dd1 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4 IR: reverse propagate int32 truncation.Erik Verbruggen2013-12-042-0/+30
| | | | | Change-Id: I5cb0c7798d0e530f3137710bf0e723bd7b64dc89 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Fix ASSERT_VALID_CODE_POINTER for our ARM buildsSimon Hausmann2013-10-171-4/+2
| | | | | | | | | | | We want to allow intermixing thumb and ARM for all builds, not only Android. Modified the macro to do a thumb-compatible null pointer check. This also works around a miscompilation on QNX where the compiler appeared to make incorrect assumptions about the address of functions we are taking. Change-Id: Ib8fc400178e0c2621bde2ca94b3f94041591e19a Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Speed up stack trace generation for the JITSimon Hausmann2013-10-162-0/+10
| | | | | | | | | | | | | | It turns out that in QML it is not unusual that during early binding evaluations due to the undefined order, the evaluation tries to look up properties in objects that aren't initialized yet and thus exceptions are thrown. Eeach thrown exception saves a stack trace, which is expensive to generate when using the JIT, as it does full stack unwinding. This patch implements a more light-weight approach by storing the instruction pointer in the context before leaving JIT generated code. Change-Id: I95e1cfd01179247dfc2c1df949828f474a23161b Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Optimise code generation for convertTypeToSInt32Lars Knoll2013-10-113-2/+35
| | | | | | | | Add 64 bit code patch and avoid some duplicated calculation in 32 bit mode Change-Id: I0e111de8ac4e733aa8802c49b4b15d785688d7ea Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: implement convertUInt32ToDouble on ARMv7.Erik Verbruggen2013-10-032-0/+12
| | | | | Change-Id: I11caf07a8776bb2c6527639f22d47103f4ca1cef Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4: invert conditions when the true block follows the test.Erik Verbruggen2013-10-031-1/+1
| | | | | Change-Id: I5044acd4263b71734e4eb5d7e74b1a4a8414741e Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Removed strange character from MacroAssemblerARM.cpp file.Tomasz Olszak2013-09-171-1/+1
| | | | | | | | | | It caused: error: stray ‘\302’ in program error: stray ‘\304’ in program when cross-compiling for ARM with gcc 4.5 Change-Id: Ibd80a21b436b65b355181b1e304ade22f9ff7404 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: generate code for binary expressions.Erik Verbruggen2013-09-111-0/+6
| | | | | Change-Id: If32ee3528fa0b6a2d04263d6c6abe1d34053d658 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Generate code conversion to double.Erik Verbruggen2013-08-281-6/+4
| | | | | | | | Performance improves by about 15% on fact.3.js when Qt is build in debug mode. Change-Id: I4a1c868fe211c1e0f9e7d9a5652f7726b37405d1 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Change convertUInt32ToDouble to use an int scratch register.Erik Verbruggen2013-08-202-10/+12
| | | | | | | Only on X86, and still untested. Change-Id: I746daa47ed019ce0017a67a228a719983b1ebaa6 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Added convertUInt32ToDouble for X86(_64)Erik Verbruggen2013-07-303-0/+28
| | | | | Change-Id: Ie6c918730d0ece0e9e63254ae97c257ee013f2f4 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Follow-up to previous commit about forcing thumb builds:Simon Hausmann2013-07-052-2/+5
| | | | | | | | | | Disable the checks of the thumb bit in code pointers when building for Android, because we want to allow for intermixing of thumb (what the JIT generates) and arm code (what the compiler generates for run-time functions we call, in debug builds) Change-Id: I0bcce4015d18db4e38244a1d1ad89413b3f17152 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Fix build on Android (part 2)Simon Hausmann2013-06-241-1/+1
| | | | | | | Don't include linux kernel headers from user space just for one constant :) Change-Id: Ia760b3f0cccbdad49f3f2ce31598a109b63ac788 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Fix build with traditional (non-thumb2) ARMSimon Hausmann2013-06-241-4/+4
| | | | | | | | Pull in the BSD licensed SegmentedVector (that is based on Vector) and use malloc/free instead of fastMalloc/fastFree in the constant pool. Change-Id: I25aeb34a6f778f2c886a331851d8fc1dd0fc1d61 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Fix build on iOSTor Arne Vestbø2013-04-171-0/+4
| | | | | | | | | | | | Add missing include for sys_cache_control, and make sure we don't define PLATFORM(IOS) or PLATFORM(IOS_SIMULATOR), since we're PLATFORM(QT). Intentionally squashed both changes for easier rebasing against upstream. Change-Id: I2e010aec76d1f1863d177af8a70091cc88bbc999 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Apply modifications on top of WTF/JSCSimon Hausmann2013-04-122-2/+9
| | | | | | | | | * Extend FunctionPtr by another overloaded constructor that allows passing 6 arguments * Work around STL <> WTF incompatibilities with iterators * Remove unused printInternal functions that rely on CString/WTFString Change-Id: Ie0cc503288871cb594716e47e03dd509b1b5ac85 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* WTF/JSC update to r148273Simon Hausmann2013-04-1215-156/+845
| | | | | | | | | | | | | This brings in various bug fixes in the ARM and MIPS assemblers as well as a Yarr crash fix and performance fix. This change doesn't compile as-is, but the next change will apply the modifications necessary to compile. That'll make future updates easier as it allows for cherry-picking because the modifications are usually always the same. Change-Id: Iac32f62c71e8ff908deb41f28f12fbc98c0823e1 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Converted calling runtime functions to new calling conventionSimon Hausmann2013-02-141-0/+7
| | | | | Change-Id: I03837e9b392957bd64a6710c1b85b4429556ba06 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Say hello to QtV4 module.Jędrzej Nowacki2013-01-3025-0/+24650
Change-Id: I507cd5707b7d7223a0d901cf939896fb2649b684 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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