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This uses the JavaScriptCore assembler rev. 195098. It is tested on iOS
(for which it is disabled, as it only allows marking pages as executable when
running from Xcode). Testing on Linux will be done when hardware
arrives.
Change-Id: I650e15fec03c27d4b326a2d70863a89b85cfc5c3
Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
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Change-Id: I2fee1d9d8c9b6437e6237388f2b0d93243fe601d
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Do not generate constant shifts of 0. We do not use the flags, so it's a
move. On ARM it's actually important not to do this, because lsr/asr
with imm=0 is a special case (shift of 32 bits).
When in the area, also skip generating an and of the second operand with
0x1f. For Intel this is done on the CPU, and for ARM the JSC assembler
will generate it for us.
This patch also updates the ARM disassembler to print the right
immediate values for the shifts.
Change-Id: I7c92c8d899352712c84e5534c48392d75466be0e
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Added VADD/VSUB/VLDR/VSTR.
Change-Id: I25fbb338652c3457e15cc9ef17209d35c63fefe5
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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This is a special-case instruction, where the immediate needs to be
multiplied by 4.
Change-Id: I86e5ab9d39d65b8eab99fae859969896c6e5630c
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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rt is on position 12. See A8.8.345.
Change-Id: Ibf380b9bda8d2edd603857935d6c92cd89d0f104
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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Ported the ARM disassembler from upstream trunk. QtQml needs to be configured
with qmake CONFIG+=disassembler and QV4_SHOW_ASM=1 enables the dump at
run-time.
Change-Id: Ia13a98835829fde0d3c5a795cb8f6ef9de951807
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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