| Commit message (Collapse) | Author | Age | Files | Lines |
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This uses the JavaScriptCore assembler rev. 195098. It is tested on iOS
(for which it is disabled, as it only allows marking pages as executable when
running from Xcode). Testing on Linux will be done when hardware
arrives.
Change-Id: I650e15fec03c27d4b326a2d70863a89b85cfc5c3
Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
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Add a rudimentary disassembler for mips32 instruction set.
Although few instructions might be missing, the whole set from
MacroAssemblerMIPS should be covered.
Change-Id: I9b1b9b40537b99098ca65036f671651d04fe1ab6
Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
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Change-Id: I2fee1d9d8c9b6437e6237388f2b0d93243fe601d
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Platforms and/or compilers have different opinions on the type of
uint64_t, so with a bit of casting and using the biggest possible
format, the warnings will hopefully disappear.
Change-Id: I1e128eaf8bc53771a517490292f52084046574dd
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Do not generate constant shifts of 0. We do not use the flags, so it's a
move. On ARM it's actually important not to do this, because lsr/asr
with imm=0 is a special case (shift of 32 bits).
When in the area, also skip generating an and of the second operand with
0x1f. For Intel this is done on the CPU, and for ARM the JSC assembler
will generate it for us.
This patch also updates the ARM disassembler to print the right
immediate values for the shifts.
Change-Id: I7c92c8d899352712c84e5534c48392d75466be0e
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Change-Id: Iba3860ef8ea940b8f232e21e273b0ac83d895882
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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The previous patch contained the wrong formatting string for 64bit
platforms. Good compilers will warn on this (and fail compiling with
-Werror). Fixed the issue in such a way that we now have static checking
for both 32bit/64bit platforms by the compiler.
Change-Id: Idf4a80d8795605c61ef812426c9984df1ceac4d4
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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The addresses were truncated to 32bits, which is a problem on win64,
because JITted code ended up outside that range.
Change-Id: I0d8b92486714340dffe4b4c2de29cf11a929a149
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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Tested on both win32 and win64.
Change-Id: I47755e2da51829e61e1452eaaf84a057224b478b
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
Reviewed-by: Gunnar Sletta <gunnar.sletta@jollamobile.com>
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Change-Id: I55a2a96a1a774c79cc2146c6b47d441fede1d102
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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Added VADD/VSUB/VLDR/VSTR.
Change-Id: I25fbb338652c3457e15cc9ef17209d35c63fefe5
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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This is a special-case instruction, where the immediate needs to be
multiplied by 4.
Change-Id: I86e5ab9d39d65b8eab99fae859969896c6e5630c
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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rt is on position 12. See A8.8.345.
Change-Id: Ibf380b9bda8d2edd603857935d6c92cd89d0f104
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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Ported the ARM disassembler from upstream trunk. QtQml needs to be configured
with qmake CONFIG+=disassembler and QV4_SHOW_ASM=1 enables the dump at
run-time.
Change-Id: Ia13a98835829fde0d3c5a795cb8f6ef9de951807
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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This brings in various bug fixes in the ARM and MIPS assemblers as well as
a Yarr crash fix and performance fix.
This change doesn't compile as-is, but the next change will
apply the modifications necessary to compile. That'll make future updates
easier as it allows for cherry-picking because the modifications are usually
always the same.
Change-Id: Iac32f62c71e8ff908deb41f28f12fbc98c0823e1
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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Change-Id: I507cd5707b7d7223a0d901cf939896fb2649b684
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
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