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path: root/src/qml/compiler/qv4regalloc.cpp
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* Remove unused code to generate post increment and decrement expressionsLars Knoll2013-09-121-8/+0
| | | | | | | | We generate lower level code in codegen and don't use these runtime methods anymore. Change-Id: If1023ce5295431305f4528839bcf2a3031fa7ad2 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 regalloc: correct life-time hole handling.Erik Verbruggen2013-09-121-4/+17
| | | | | | | | | | | | When a life-range is active, but does not cover a position, it means that it is inactive. When going from active to inactive (or vice-versa), a (un-)spill is only needed when there is a stack-slot allocated to the range. It is valid to not have a stack slot: when no call is done, or when the register pressure does not push the end of the hole onto the stack. Change-Id: I5f5a05181c8cb384f031538dbefd7d11de682b8d Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4 regalloc: fix cycle scheduling in resolve phase.Erik Verbruggen2013-09-121-17/+17
| | | | | | | | | | | | When resolving differences in register/spill-slot assignment between basic-blocks, dependency cycles can occur. Those cycles have to be scheduled after non-cyclic dependencies. This also removes a assertion that only held when the cycle was 2 long, but would incorrectly fire for longer cycles. Change-Id: I519fd43bbf117d3480e4169ff363e97a9ec450f8 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4 JIT: generate code for binary expressions.Erik Verbruggen2013-09-111-0/+7
| | | | | Change-Id: If32ee3528fa0b6a2d04263d6c6abe1d34053d658 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4: Fix build in release with forced assertsKonstantin Ritt2013-09-101-1/+1
| | | | | Change-Id: I7419b10223ebb28cc54cbb595818509a7384ac6a Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4 regalloc: loading this never needs/needed a call.Erik Verbruggen2013-09-101-1/+0
| | | | | Change-Id: Ibf95a5fe7634094386ba103b01b4e7e9f2c183e8 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Generate code for conversion to signed int32.Erik Verbruggen2013-08-291-3/+5
| | | | | Change-Id: I862a8c9c262b658859cc9b57ea0b6e9eb60e32e5 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Generate code for conversion to boolean.Erik Verbruggen2013-08-291-1/+2
| | | | | Change-Id: I59e24264325b6560ee1c0dbdafacb1f08c3671d5 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 regalloc: fix off-by-one in availability calculation.Erik Verbruggen2013-08-281-26/+10
| | | | | | | | | Simplified the algorithm, and use it to iterate over all registers. The previous version did not initialize bestReg correctly, thereby skipping the first register (which could also be the best one). Change-Id: I7e33f93a27e8fe64cd00acac755cf67ca5f0b1b8 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 regalloc: do not overwrite register availability in hole.Erik Verbruggen2013-08-281-1/+1
| | | | | | | | | | | When a fixed interval for a register is inactive, the register is free until that interval becomes active, or (and this was missing), until another interval uses it before that position. So instead of blindly overwriting the freeUntilPos, take the qMin of the existing one with the intersection position. Change-Id: I2730a748ef1e46b4782fbb9814e800eca52172f0 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Generate code conversion to double.Erik Verbruggen2013-08-281-2/+2
| | | | | | | | Performance improves by about 15% on fact.3.js when Qt is build in debug mode. Change-Id: I4a1c868fe211c1e0f9e7d9a5652f7726b37405d1 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* The fast and the furious, register drift.Erik Verbruggen2013-08-271-25/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable the register allocator for X86_64 on Linux and MacOS. The implications are: - handle as much as possible with current code with as few changes as possible - temporarily force the register allocator to spill unop/binop arguments to the stack by doing a call in the implementation (as is the current case), so no change is needed here - only have loadThis and loadConst handle registers - have any method that might need to handle registrers actually cope with them - the inline versions of binops are not generated, as they cannot cope with registers. This will change when ISel for binops is added in the next patch. This means that we are still running with the handbrakes on, but allow for full-throttle in certain/limited cases. Note about the changed test: multiplication always returns a Number (double), so the operands are passed as doubles, so __qmljs_mul will return a double. For addition this is different: because it might return a Number or a String, the operands are passed as whatever fits best. So __qmljs_add will return an int when both operands are ints. Hence the change to the tests. Change-Id: If5bd7dffca8f7de5ba45af700b9c7bb568fc74b7 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Add linear scan register allocation.Erik Verbruggen2013-08-191-0/+1628
Currently disabled for all platforms. Will be enabled step-by-step when specific platforms get supported. Change-Id: I144c6c991b1666e1ff752d776bca0a7b57a4fe7c Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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