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* V4: fix failing tests for right shifts over 0 bits on non-Intel.Erik Verbruggen2015-06-191-22/+41
| | | | | Change-Id: I6a0428be2b81cb6723b591356f78712ef2cc0b8b Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* V4: add JIT support for mips platforms (32-bit) and enable itJulien Brianceau2015-04-271-2/+2
| | | | | | | [ChangeLog][QtQml] Enabled Just-In-Time compilation for JavaScript on MIPS Change-Id: Idce070f29645760d6376767ef67e4592828c104d Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* Merge remote-tracking branch 'origin/5.4' into 5.5Liang Qi2015-04-161-2/+2
|\ | | | | | | | | | | | | | | Conflicts: tests/auto/qml/debugger/qv4profilerservice/qv4profilerservice.pro tests/auto/qml/debugger/qqmldebuggingenabler/qqmldebuggingenabler.pro Change-Id: I76d87e3df97ebdba902ca3d7488c1582eca2a83c
| * V4 JIT: fix typo in Binop::int32BinopJulien Brianceau2015-04-141-2/+2
| | | | | | | | | | Change-Id: I68f073ab512b482c9b3b1ad7860f4c759245298e Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* | Update copyright headersJani Heikkinen2015-02-121-7/+7
| | | | | | | | | | | | | | | | | | Qt copyrights are now in The Qt Company, so we could update the source code headers accordingly. In the same go we should also fix the links to point to qt.io. Change-Id: I61120571787870c0ed17066afb31779b1e6e30e9 Reviewed-by: Iikka Eklund <iikka.eklund@theqtcompany.com>
* | Change signature or runtime methods to take an engine pointerLars Knoll2014-11-121-1/+1
|/ | | | | | | | | This makes a lot more sense in the long term and is the more maintainable solution, once the GC starts moving objects around in memory Change-Id: I8f327c0f5b5b0af38c5fe1a217852ee8c4a5c2fc Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Update license headers and add new licensesJani Heikkinen2014-08-251-19/+11
| | | | | | | | | - Renamed LICENSE.LGPL to LICENSE.LGPLv21 - Added LICENSE.LGPLv3 & LICENSE.GPLv2 - Removed LICENSE.GPL Change-Id: I84a565e2e0caa3b76bf291a7d188a57a4b00e1b0 Reviewed-by: Jani Heikkinen <jani.heikkinen@digia.com>
* V4 JIT: tune generated instructions for inplace binopsErik Verbruggen2014-08-121-183/+242
| | | | | | | | | | Generate better code for in-place binary operations where the right-hand side is either a constant or a memory address. Now that the JIT can do this, also tell the register allocator not to un-spill that right-hand side. Change-Id: I0ab852f6b92f90dfed99c05fbaf91aad2549ecf4 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4: Split arguments/locals from temps.Erik Verbruggen2014-05-231-22/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a couple of reasons to split the temporaries off from the arguments and locals: Temporaries are invisible, and changes to them cannot be observed. On the other hand, arguments and locals are visible, and writes to them can be seen from other places (nested functions), or by using the arguments array. So, in practice these correspond to memory locations. (One could argue that if neither nested functions, nor eval(), nor arguments[] is used, the loads/stores are invisible too. But that's an optimization, and changing locals/arguments to temporaries can be done in a separate pass.) Because of the "volatile" nature of arguments and locals, their usage cannot be optimized. All optimizations (SSA construction, register allocation, copy elimination, etc.) work on temporaries. Being able to easily ignore all non-temporaries has the benefit that optimizations can be faster. Previously, Temps were not uniquely numbered: argument 1, local 1, and temporary 1 all had the same number and were distinguishable by their type. So, for any mapping from Temp to something else, a QHash was used. Now that Temps only hold proper temporaries, the indexes do uniquely identify them. Add to that the fact that after transforming to SSA form all temporaries are renumbered starting from 0 and without any holes in the numbering, many of those datastructures can be changed to simple vectors. That change gives a noticeable performance improvement. One implication of this change is that a number of functions that took a Temp as their argument, now need to take Temp-or-ArgLocal, so Expr. However, it turns out that there are very few places where that applies, as many of those places also need to take constants or names. However, explicitly separating memory loads/stores for arguments/locals from temporaries adds the benefit that it's now easier to do a peep-hole optimizer for those load/store operations in the future: when a load is directly preceded by a store, it can be eliminated if the value is still available in a temporary. Change-Id: I4114006b076795d9ea9fe3649cdb3b9d7b7508f0 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: fix constant shifts.Erik Verbruggen2014-04-151-8/+28
| | | | | | | | | | | | | | | | Do not generate constant shifts of 0. We do not use the flags, so it's a move. On ARM it's actually important not to do this, because lsr/asr with imm=0 is a special case (shift of 32 bits). When in the area, also skip generating an and of the second operand with 0x1f. For Intel this is done on the CPU, and for ARM the JSC assembler will generate it for us. This patch also updates the ARM disassembler to print the right immediate values for the shifts. Change-Id: I7c92c8d899352712c84e5534c48392d75466be0e Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Fix wrong register usage for integer binopsSimon Hausmann2014-04-081-23/+8
| | | | | | | | | | | | | | | | | | | | | | When doing of integers where we use a three argument variant of masm (lhs/rhs/target), we need three general purpose registers. If the target temp of the binop is a register, we use that as a target, otherwise fall back to ReturnValueRegister (scratch). In that case we don't need to move from RVR to target register. Additionally we need to load lhs and rhs into registers, and for the lhs we use the target register and for the rhs the scratch register. So we start by loading the lhs into the target register and the rhs into the scratch register. However if the rhs is already assigned to a register and that register happens to be the target register, then the earlier load of the lhs into the target register overwrote our rhs! This is fixed by being more careful in the choice of the target temp's assigned register as "scratch" register for the lhs, i.e. don't use it if the target temp is also assigned to the same register as the rhs. Task-number: QTBUG-38097 Change-Id: I2ffec55cb98818fa9ebb5a76a32b6dca72175893 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Use Q_ASSERT instead of assertLars Knoll2014-03-191-1/+1
| | | | | Change-Id: I6185b59a7dfd6977ce82581ab4385e07d78f13f6 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Cleanup our runtime methodsLars Knoll2014-03-111-22/+22
| | | | | | | | | Move all our runtime methods into the QV4::Runtime struct and give them nicer names without underscores. Sort them logically and remove a few unused methods. Change-Id: Ib69b71764ff194d0ba211aac581f9a99734d8180 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Move all binop related code into qv4binop*Lars Knoll2014-03-041-2/+59
| | | | | Change-Id: I8f96b8d570dd4c0139b0a2e595055b3b2c6dae70 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Clean up our internal namespacesLars Knoll2014-02-231-71/+68
| | | | | | | | QQmlJS::MASM -> QV4::JIT QQmlJS::V4IR -> QV4::IR Change-Id: I707e8990459114a699c200fe3c22cec3c8df1afc Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Move binops out of the iselLars Knoll2014-02-221-0/+431
Move the binop handling into qv4binop* to clean up the code and ease maintenance. Change-Id: I0053380be7f326a2100302a63e921698a5b28c2a Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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