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* Add missing "We mean it" comments to private headers.Friedemann Kleint2015-10-061-0/+11
| | | | | | Task-number: QTBUG-48594 Change-Id: Ifc207938de7f0c8995fc712df92665f222612647 Reviewed-by: Alan Alpert <aalpert@blackberry.com>
* V4: add JIT support for mips platforms (32-bit) and enable itJulien Brianceau2015-04-271-0/+65
| | | | | | | [ChangeLog][QtQml] Enabled Just-In-Time compilation for JavaScript on MIPS Change-Id: Idce070f29645760d6376767ef67e4592828c104d Reviewed-by: Simon Hausmann <simon.hausmann@theqtcompany.com>
* Update copyright headersJani Heikkinen2015-02-121-7/+7
| | | | | | | | | Qt copyrights are now in The Qt Company, so we could update the source code headers accordingly. In the same go we should also fix the links to point to qt.io. Change-Id: I61120571787870c0ed17066afb31779b1e6e30e9 Reviewed-by: Iikka Eklund <iikka.eklund@theqtcompany.com>
* V4 JIT: ARM: move registers around.Erik Verbruggen2015-01-121-2/+2
| | | | | | | | | | | | | | | | In 6572d4e50d73ac60a8974d07de74c27a7f99ebef we moved the addressTempRegister to r10, and in d8b276a59402cbbe6d070ba38805350e7f3dd8a1 we made sure that the YarrJIT saves it too. JSC solved this by moving it to r6, which is already saved by the YarrJIT. To make a future update of the assembler easier, we also move it to r6. This requires that we move our scratch register too. But, because it is used a lot, we don't want it above r7 for Thumb2 reasons. Therefore, we move the engine to r10, and the scratch register to r5. Change-Id: I35be539940d9fe80971973cfa7f3a8dab2196a1e Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Change signature or runtime methods to take an engine pointerLars Knoll2014-11-121-4/+4
| | | | | | | | | This makes a lot more sense in the long term and is the more maintainable solution, once the GC starts moving objects around in memory Change-Id: I8f327c0f5b5b0af38c5fe1a217852ee8c4a5c2fc Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Update license headers and add new licensesJani Heikkinen2014-08-251-18/+10
| | | | | | | | | - Renamed LICENSE.LGPL to LICENSE.LGPLv21 - Added LICENSE.LGPLv3 & LICENSE.GPLv2 - Removed LICENSE.GPL Change-Id: I84a565e2e0caa3b76bf291a7d188a57a4b00e1b0 Reviewed-by: Jani Heikkinen <jani.heikkinen@digia.com>
* V4 JIT: add d8-d15 as available FP registers on ARM.Erik Verbruggen2014-08-141-1/+8
| | | | | | | | | | VFP3-d16 is the minimum implementation available on ARMv7, so these registers are also always available. The big added bonus is that they are callee saved, so using them will result in less loads/stores for doubles. Change-Id: I0cab3fe24d8677315b4c7d9449d8619cbf9a2919 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: parameterize the prologue and epilogue generationErik Verbruggen2014-08-141-24/+0
| | | | | | | | | ... with the regular (non-FP) registers that need to be saved. This patch shouldn't change any of the JIT generated code, because all regular callee saved registers are passed in. Change-Id: Id11b8f37f06d80e8015ac6f0d0ccefdfa3342cbe Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* Make sure JIT architectures lists are in syncDmitry Shachnev2014-07-071-1/+3
| | | | | | | | | We have two lists: in qv4global_p.h and qv4targetplatform_p.h. This commit blacklists OSes on x86 and x86_64 where JIT is not supported, improves support for FreeBSD and adds cross-references between these two files. Change-Id: Id3715a2ab717186e510a54e5a548dfa22120cd87 Reviewed-by: Erik Verbruggen <erik.verbruggen@digia.com>
* V4 JIT: teach regalloc about callee-saved registers.Erik Verbruggen2014-06-171-1/+14
| | | | | | | | Callee-saved registers won't get clobbered by a call, so any value stored in it will survive the call. Change-Id: I2b61b84617b01bf7ce7e81cd0119a6da689ee9d5 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
* V4 JIT: use RegisterInfo in the register allocator.Erik Verbruggen2014-06-131-26/+0
| | | | | Change-Id: Ia9faeb20b360f41d00f908132fd306e2d25c7574 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* Add FreeBSD support to qv4targetplatform_p.hDmitry Shachnev2014-06-101-2/+2
| | | | | | | | Currently, that code only works on Linux, Windows, Mac OS X and QNX on x86 and x86_64 processors. Change-Id: I07f2cb4cb9b8556d4bcd681c6a1f997dc3897901 Reviewed-by: Thiago Macieira <thiago.macieira@intel.com>
* V4: add back HAVE_ALU_OPS_WITH_MEM_OPERAND.Erik Verbruggen2014-05-261-0/+4
| | | | | | | | This macro accidentally got dropped by ddb33ee9ba9e1344caa9be5dbf4b534c3ede692e. Change-Id: I154b89df106de37c53e52c1c449bd4eabadde861 Reviewed-by: Lars Knoll <lars.knoll@digia.com>
* V4: Fix compilation failure on BB10 x86 and QNX6 x86Sergio Ahumada2014-05-261-2/+2
| | | | | | | | This change amends ddb33ee9ba9e1344caa9be5dbf4b534c3ede692e Task-number: QTBUG-39274 Change-Id: If0c3bc1204433315b9329229304db7ddadc785f2 Reviewed-by: Erik Verbruggen <erik.verbruggen@digia.com>
* V4: clean-up target specific register definitions and stack usageErik Verbruggen2014-05-241-0/+397
All constants referring to registers and all constants and functions that do platform specific things with the stack, are all modev into a separate file. Information about how a specific platform register is used by the ABI is also extended and is now captured in the RegisterInfo class. Usage of this information will be extended in subsequent patches. This also fix ARM register usage: - Correct fp register for Thumb mode. - Only push registers that have to be saved and will actually be used from the stack (i.e. do not push r0-r3 in the function prelude). Change-Id: Ia372505ade8f2648595c7aec1d281955392f34a1 Reviewed-by: Simon Hausmann <simon.hausmann@digia.com>
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