From ca402cfe7e03d1f9a8d5cb47130e37a481c9e30a Mon Sep 17 00:00:00 2001 From: Simon Hausmann Date: Wed, 18 Jan 2017 11:55:59 +0100 Subject: Correctly specialize TargetPlatform as template Change-Id: I37d2a2d74e150b92f5a338d799def337dcb8abd9 Reviewed-by: Lars Knoll --- src/qml/jit/qv4assembler.cpp | 2 +- src/qml/jit/qv4assembler_p.h | 29 +++++++--- src/qml/jit/qv4binop.cpp | 2 +- src/qml/jit/qv4isel_masm_p.h | 2 +- src/qml/jit/qv4targetplatform_p.h | 108 ++++++++++++++++++++++++++++---------- src/qml/jit/qv4unop.cpp | 2 +- 6 files changed, 105 insertions(+), 40 deletions(-) (limited to 'src/qml') diff --git a/src/qml/jit/qv4assembler.cpp b/src/qml/jit/qv4assembler.cpp index e4defae802..3800307de0 100644 --- a/src/qml/jit/qv4assembler.cpp +++ b/src/qml/jit/qv4assembler.cpp @@ -687,6 +687,6 @@ JSC::MacroAssemblerCodeRef Assembler::link(int *codeSize) return codeRef; } -template class QV4::JIT::Assembler>; +template class QV4::JIT::Assembler; #endif diff --git a/src/qml/jit/qv4assembler_p.h b/src/qml/jit/qv4assembler_p.h index ddd1463cec..308f31e97a 100644 --- a/src/qml/jit/qv4assembler_p.h +++ b/src/qml/jit/qv4assembler_p.h @@ -90,30 +90,43 @@ struct CompilationUnit : public QV4::CompiledData::CompilationUnit QVector codeRefs; }; +template +struct AssemblerTargetConfiguration +{ + typedef JSC::MacroAssembler MacroAssembler; + typedef TargetPlatform Platform; + // More things coming here in the future, such as Target OS +}; + #if CPU(ARM_THUMB2) typedef JSC::MacroAssemblerARMv7 DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #elif CPU(ARM64) typedef JSC::MacroAssemblerARM64 DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #elif CPU(ARM_TRADITIONAL) typedef JSC::MacroAssemblerARM DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #elif CPU(MIPS) typedef JSC::MacroAssemblerMIPS DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #elif CPU(X86) typedef JSC::MacroAssemblerX86 DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #elif CPU(X86_64) typedef JSC::MacroAssemblerX86_64 DefaultPlatformMacroAssembler; + +#if OS(WINDOWS) +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; +#else +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; +#endif + #elif CPU(SH4) typedef JSC::MacroAssemblerSH4 DefaultPlatformMacroAssembler; +typedef AssemblerTargetConfiguration DefaultAssemblerTargetConfiguration; #endif -template -struct AssemblerTargetConfiguration -{ - typedef JSC::MacroAssembler MacroAssembler; - typedef TargetPlatform Platform; - // More things coming here in the future, such as Target OS -}; - #define isel_stringIfyx(s) #s #define isel_stringIfy(s) isel_stringIfyx(s) diff --git a/src/qml/jit/qv4binop.cpp b/src/qml/jit/qv4binop.cpp index dfaf7f518c..3a349286c6 100644 --- a/src/qml/jit/qv4binop.cpp +++ b/src/qml/jit/qv4binop.cpp @@ -576,6 +576,6 @@ typename JITAssembler::Jump Binop::genInlineBinop(IR::Expr *leftSo return done; } -template struct QV4::JIT::Binop>>; +template struct QV4::JIT::Binop>; #endif diff --git a/src/qml/jit/qv4isel_masm_p.h b/src/qml/jit/qv4isel_masm_p.h index 8dcf5da900..1e5fde4502 100644 --- a/src/qml/jit/qv4isel_masm_p.h +++ b/src/qml/jit/qv4isel_masm_p.h @@ -72,7 +72,7 @@ QT_BEGIN_NAMESPACE namespace QV4 { namespace JIT { -template >> +template > class Q_QML_EXPORT InstructionSelection: protected IR::IRDecoder, public EvalInstructionSelection diff --git a/src/qml/jit/qv4targetplatform_p.h b/src/qml/jit/qv4targetplatform_p.h index 97401fbaa5..ca6da649c9 100644 --- a/src/qml/jit/qv4targetplatform_p.h +++ b/src/qml/jit/qv4targetplatform_p.h @@ -63,6 +63,11 @@ QT_BEGIN_NAMESPACE namespace QV4 { namespace JIT { +enum TargetOperatingSystemSpecialization { + NoOperatingSystemSpecialization, + WindowsSpecialization +}; + // The TargetPlatform class describes how the stack and the registers work on a CPU+ABI combination. // // All combinations have a separate definition, guarded by #ifdefs. The exceptions are: @@ -79,14 +84,20 @@ namespace JIT { // a call, we add a load it right before emitting the call instruction. // // NOTE: When adding new architecture, do not forget to whitelist it in qv4global_p.h! -template +template class TargetPlatform { -public: - using RegisterID = typename PlatformAssembler::RegisterID; - using FPRegisterID = typename PlatformAssembler::FPRegisterID; +}; #if CPU(X86) && (OS(LINUX) || OS(WINDOWS) || OS(QNX) || OS(FREEBSD) || defined(Q_OS_IOS)) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerX86; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; + enum { RegAllocIsSupported = 1 }; static const RegisterID FramePointerRegister = JSC::X86Registers::ebp; @@ -100,10 +111,10 @@ public: static const RegisterID LowReturnValueRegister = JSC::X86Registers::eax; static const RegisterID HighReturnValueRegister = JSC::X86Registers::edx; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() << RI(JSC::X86Registers::edx, QStringLiteral("edx"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::X86Registers::ebx, QStringLiteral("ebx"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::X86Registers::edi, QStringLiteral("edi"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) @@ -115,6 +126,7 @@ public: << RI(JSC::X86Registers::xmm6, QStringLiteral("xmm6"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::X86Registers::xmm7, QStringLiteral("xmm7"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) ; + return info; } # define HAVE_ALU_OPS_WITH_MEM_OPERAND 1 @@ -135,7 +147,7 @@ public: ((OS(LINUX) || OS(FREEBSD)) && (defined(__PIC__) || defined(__PIE__))) #define RESTORE_EBX_ON_CALL - using Address = typename PlatformAssembler::Address; + using Address = PlatformAssembler::Address; static Address ebxAddressOnStack() { static int ebxIdx = -1; @@ -156,10 +168,18 @@ public: return Address(FramePointerRegister, ebxIdx * -int(sizeof(void*))); } #endif - -#endif // Windows on x86 +}; +#endif // x86 #if CPU(X86_64) && (OS(LINUX) || OS(MAC_OS_X) || OS(FREEBSD) || OS(QNX) || defined(Q_OS_IOS)) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerX86_64; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; + enum { RegAllocIsSupported = 1 }; static const RegisterID FramePointerRegister = JSC::X86Registers::ebp; @@ -171,10 +191,10 @@ public: static const FPRegisterID FPGpr0 = JSC::X86Registers::xmm0; static const FPRegisterID FPGpr1 = JSC::X86Registers::xmm1; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() << RI(JSC::X86Registers::ebx, QStringLiteral("rbx"), RI::RegularRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::X86Registers::edi, QStringLiteral("rdi"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::X86Registers::esi, QStringLiteral("rsi"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) @@ -192,6 +212,7 @@ public: << RI(JSC::X86Registers::xmm6, QStringLiteral("xmm6"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::X86Registers::xmm7, QStringLiteral("xmm7"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) ; + return info; } #define HAVE_ALU_OPS_WITH_MEM_OPERAND 1 @@ -219,9 +240,18 @@ public: static const int StackSpaceAllocatedUponFunctionEntry = RegisterSize; // Return address is pushed onto stack by the CPU. static void platformEnterStandardStackFrame(PlatformAssembler *as) { as->push(FramePointerRegister); } static void platformLeaveStandardStackFrame(PlatformAssembler *as) { as->pop(FramePointerRegister); } +}; #endif // Linux/MacOS on x86_64 #if CPU(X86_64) && OS(WINDOWS) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerX86_64; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; + // Register allocation is not (yet) supported on win64, because the ABI related stack handling // is not completely implemented. Specifically, the saving of xmm registers, and the saving of // incoming function parameters to the shadow space is missing. @@ -236,10 +266,10 @@ public: static const FPRegisterID FPGpr0 = JSC::X86Registers::xmm0; static const FPRegisterID FPGpr1 = JSC::X86Registers::xmm1; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() << RI(JSC::X86Registers::ebx, QStringLiteral("rbx"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::edi, QStringLiteral("rdi"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::esi, QStringLiteral("rsi"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) @@ -251,6 +281,7 @@ public: << RI(JSC::X86Registers::r14, QStringLiteral("r14"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) << RI(JSC::X86Registers::r15, QStringLiteral("r15"), RI::RegularRegister, RI::CalleeSaved, RI::Predefined) ; + return info; } #define HAVE_ALU_OPS_WITH_MEM_OPERAND 1 @@ -276,9 +307,18 @@ public: static const int StackSpaceAllocatedUponFunctionEntry = RegisterSize; // Return address is pushed onto stack by the CPU. static void platformEnterStandardStackFrame(PlatformAssembler *as) { as->push(FramePointerRegister); } static void platformLeaveStandardStackFrame(PlatformAssembler *as) { as->pop(FramePointerRegister); } +}; #endif // Windows on x86_64 #if CPU(ARM) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerARMv7; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; + enum { RegAllocIsSupported = 1 }; // The AAPCS specifies that the platform ABI has to define the usage of r9. Known are: @@ -309,10 +349,10 @@ public: static const RegisterID LowReturnValueRegister = JSC::ARMRegisters::r0; static const RegisterID HighReturnValueRegister = JSC::ARMRegisters::r1; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() << RI(JSC::ARMRegisters::r0, QStringLiteral("r0"), RI::RegularRegister, RI::CallerSaved, RI::Predefined) << RI(JSC::ARMRegisters::r1, QStringLiteral("r1"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::ARMRegisters::r2, QStringLiteral("r2"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) @@ -345,6 +385,7 @@ public: << RI(JSC::ARMRegisters::d14, QStringLiteral("d14"), RI::FloatingPointRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::ARMRegisters::d15, QStringLiteral("d15"), RI::FloatingPointRegister, RI::CalleeSaved, RI::RegAlloc) ; + return info; } #undef HAVE_ALU_OPS_WITH_MEM_OPERAND @@ -381,9 +422,18 @@ public: as->pop(FramePointerRegister); as->pop(JSC::ARMRegisters::lr); } +}; #endif // ARM (32 bit) #if CPU(ARM64) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerARM64; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; + enum { RegAllocIsSupported = 1 }; static const RegisterID FramePointerRegister = JSC::ARM64Registers::fp; @@ -395,10 +445,10 @@ public: static const FPRegisterID FPGpr0 = JSC::ARM64Registers::q0; static const FPRegisterID FPGpr1 = JSC::ARM64Registers::q1; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() << RI(JSC::ARM64Registers::x0, QStringLiteral("x0"), RI::RegularRegister, RI::CallerSaved, RI::Predefined) << RI(JSC::ARM64Registers::x1, QStringLiteral("x1"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::ARM64Registers::x2, QStringLiteral("x2"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) @@ -456,6 +506,7 @@ public: << RI(JSC::ARM64Registers::q30, QStringLiteral("q30"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::ARM64Registers::q31, QStringLiteral("q31"), RI::FloatingPointRegister, RI::CallerSaved, RI::RegAlloc) ; + return info; } #undef HAVE_ALU_OPS_WITH_MEM_OPERAND @@ -494,9 +545,17 @@ public: { as->popPair(FramePointerRegister, JSC::ARM64Registers::lr); } +}; #endif // ARM64 #if defined(Q_PROCESSOR_MIPS_32) && defined(Q_OS_LINUX) +template <> +class TargetPlatform +{ +public: + using PlatformAssembler = JSC::MacroAssemblerMIPS; + using RegisterID = PlatformAssembler::RegisterID; + using FPRegisterID = PlatformAssembler::FPRegisterID; enum { RegAllocIsSupported = 1 }; static const RegisterID FramePointerRegister = JSC::MIPSRegisters::fp; @@ -510,10 +569,10 @@ public: static const RegisterID LowReturnValueRegister = JSC::MIPSRegisters::v0; static const RegisterID HighReturnValueRegister = JSC::MIPSRegisters::v1; - static RegisterInformation getPlatformRegisterInfo() + static RegisterInformation getRegisterInfo() { typedef RegisterInfo RI; - return RegisterInformation() + static RegisterInformation info = RegisterInformation() // Note: t0, t1, t2, t3 and f16 are already used by MacroAssemblerMIPS. << RI(JSC::MIPSRegisters::t4, QStringLiteral("t4"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) << RI(JSC::MIPSRegisters::t5, QStringLiteral("t5"), RI::RegularRegister, RI::CallerSaved, RI::RegAlloc) @@ -535,6 +594,7 @@ public: << RI(JSC::MIPSRegisters::f26, QStringLiteral("f26"), RI::FloatingPointRegister, RI::CalleeSaved, RI::RegAlloc) << RI(JSC::MIPSRegisters::f28, QStringLiteral("f28"), RI::FloatingPointRegister, RI::CalleeSaved, RI::RegAlloc) ; + return info; } #undef HAVE_ALU_OPS_WITH_MEM_OPERAND @@ -571,16 +631,8 @@ public: as->pop(FramePointerRegister); as->pop(JSC::MIPSRegisters::ra); } -#endif // Linux on MIPS (32 bit) - -public: // utility functions - static const RegisterInformation getRegisterInfo() - { - static const RegisterInformation info = getPlatformRegisterInfo(); - - return info; - } }; +#endif // Linux on MIPS (32 bit) } // JIT namespace } // QV4 namespace diff --git a/src/qml/jit/qv4unop.cpp b/src/qml/jit/qv4unop.cpp index 739bd97010..cc03fa6006 100644 --- a/src/qml/jit/qv4unop.cpp +++ b/src/qml/jit/qv4unop.cpp @@ -144,6 +144,6 @@ void Unop::generateCompl(IR::Expr *source, IR::Expr *target) generateRuntimeCall(_as, target, complement, PointerToValue(source)); } -template struct QV4::JIT::Unop>>; +template struct QV4::JIT::Unop>; #endif -- cgit v1.2.3