From 0640fbc8e53644facf199ab0bd3a7414cf149068 Mon Sep 17 00:00:00 2001
From: Erik Verbruggen <erik.verbruggen@me.com>
Date: Thu, 10 Oct 2013 13:34:12 +0200
Subject: V4 ARM: extend disassembler.

Added VADD/VSUB/VLDR/VSTR.

Change-Id: I25fbb338652c3457e15cc9ef17209d35c63fefe5
Reviewed-by: Lars Knoll <lars.knoll@digia.com>
---
 .../masm/disassembler/ARMv7/ARMv7DOpcode.cpp       | 41 ++++++++++++++++++++++
 .../masm/disassembler/ARMv7/ARMv7DOpcode.h         | 36 +++++++++++++++++++
 2 files changed, 77 insertions(+)

(limited to 'src')

diff --git a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp
index 81081b8fbb..81063e2b11 100644
--- a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp
+++ b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.cpp
@@ -116,8 +116,10 @@ static Opcode32GroupInitializer opcode32BitGroupList[] = {
     OPCODE_GROUP_ENTRY(0x5, ARMv7DOpcodeDataProcessingShiftedReg),
     OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVMOVSinglePrecision),
     OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVMOVDoublePrecision),
+    OPCODE_GROUP_ENTRY(0x6, ARMv7DOpcodeVLDRVSTR),
     OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeFPTransfer),
     OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeVMSR),
+    OPCODE_GROUP_ENTRY(0x7, ARMv7DOpcodeVADDVSUB),
     OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeDataProcessingModifiedImmediate),
     OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeConditionalBranchT3),
     OPCODE_GROUP_ENTRY(0x8, ARMv7DOpcodeBranchOrBranchLink),
@@ -1561,6 +1563,45 @@ const char* ARMv7DOpcodeVMSR::format()
     return m_formatBuffer;
 }
 
+const char* ARMv7DOpcodeVADDVSUB::format()
+{
+    char regPrefix = sz() ? 'd' : 's';
+    if (isSub())
+        appendInstructionName("vsub");
+    else
+        appendInstructionName("vadd");
+    appendFPRegisterName(regPrefix, vd());
+    appendSeparator();
+    appendFPRegisterName(regPrefix, vn());
+    appendSeparator();
+    appendFPRegisterName(regPrefix, vm());
+
+    return m_formatBuffer;
+}
+
+const char* ARMv7DOpcodeVLDRVSTR::format()
+{
+    appendInstructionName(opName());
+
+    char regPrefix = sz() ? 'd' : 's';
+    appendFPRegisterName(regPrefix, vd());
+
+    appendSeparator();
+    appendCharacter('[');
+    appendRegisterName(rn());
+
+    if (immediate8() || !uBit()) {
+        appendSeparator();
+        if (uBit())
+            appendUnsignedImmediate(immediate8() << 2);
+        else
+            appendSignedImmediate(0 - static_cast<int>(immediate8() << 2));
+    }
+    appendCharacter(']');
+
+    return m_formatBuffer;
+}
+
 } } // namespace JSC::ARMv7Disassembler
 
 #endif // #if USE(ARMV7_DISASSEMBLER)
diff --git a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h
index 3f1f062e44..ca5f955ba1 100644
--- a/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h
+++ b/src/3rdparty/masm/disassembler/ARMv7/ARMv7DOpcode.h
@@ -1132,6 +1132,42 @@ protected:
     unsigned rt() { return (m_opcode >> 12) & 0xf; }
 };
 
+class ARMv7DOpcodeVADDVSUB : public ARMv7D32BitOpcode {
+public:
+    static const uint32_t s_mask =    0xffb00e50;
+    static const uint32_t s_pattern = 0xee300a00;
+
+    DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVADDVSUB, thisObj);
+
+protected:
+    const char* format();
+
+    unsigned sz() { return (m_opcode >> 8) & 0x1; }
+    unsigned isSub() { return (m_opcode >> 6) & 0x1; }
+    unsigned vm() { return (m_opcode & 0xf) | ((m_opcode >> 1) & 0x10); }
+    unsigned vn() { return ((m_opcode >> 16) & 0xf) | ((m_opcode >> 3) & 0x10); }
+    unsigned vd() { return ((m_opcode >> 12) & 0xf) | ((m_opcode >> 18) & 0x10); }
+};
+
+class ARMv7DOpcodeVLDRVSTR : public ARMv7D32BitOpcode {
+public:
+    static const uint32_t s_mask =    0xff200a00;
+    static const uint32_t s_pattern = 0xed000a00;
+
+    DEFINE_STATIC_FORMAT32(ARMv7DOpcodeVLDRVSTR, thisObj);
+
+protected:
+    const char* format();
+
+    const char *opName() { return op() ? "vldr" : "vstr"; }
+
+    unsigned sz() { return (m_opcode >> 8) & 0x1; }
+    unsigned op() { return (m_opcode >> 20) & 0x1; }
+    unsigned uBit() { return (m_opcode >> 23) & 0x1; }
+    unsigned rn() { return (m_opcode >> 16) & 0xf; }
+    unsigned vd() { return ((m_opcode >> 12) & 0xf) | ((m_opcode >> 18) & 0x10); }
+    unsigned immediate8() { return m_opcode & 0xff; }
+};
 
 } } // namespace JSC::ARMv7Disassembler
 
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